PIC24FJ16MC101_12 Datasheet, PDF (185/350 Pages) Microchip Technology – 16-bit Microcontrollers (up to 32 KB Flash and 2 KB SRAM)

PIC24FJ16MC101/102 AND PIC24FJ32MC101/102/104
18.0 UNIVERSAL ASYNCHRONOUS
RECEIVER TRANSMITTER
(UART)
Note 1: This data sheet summarizes the features
of the PIC24FJ16MC101/102 and
PIC24FJ32MC101/102/104 family of
devices. It is not intended to be a
comprehensive reference source. To
complement the information in this data
sheet, refer to Section 21. “UART”
(DS39708) in the “PIC24F Family
Reference Manual”, which is available
from the Microchip web site
(www.microchip.com).
2: It is important to note that the
specifications in Section 26.0 “Electri-
cal Characteristics” of this data sheet,
supercede any specifications that may be
provided in PIC24F Family Reference
Manual sections.
3: Some registers and associated bits
described in this section may not be
available on all devices. Refer to
Section 4.0 “Memory Organization” in
this data sheet for device-specific register
and bit information.
The Universal Asynchronous Receiver Transmitter
(UART) module is one of the serial I/O modules
available in the PIC24FJ16MC101/102 and
PIC24FJ32MC101/102/104 device family. The UART is
a full-duplex asynchronous system that can
communicate with peripheral devices, such as
personal computers, LIN 2.0, and RS-232, and RS-485
interfaces. The module also supports a hardware flow
control option with the UxCTS and UxRTS pins and
also includes an IrDA^® encoder and decoder.
The primary features of the UART module are:
• Full-Duplex, 8-bit or 9-bit Data Transmission
through the UxTX and UxRX pins
• Even, Odd, or No Parity Options (for 8-bit data)
• One or two stop bits
• Hardware flow control option with UxCTS and
UxRTS pins
• Fully integrated Baud Rate Generator with 16-bit
prescaler
• Baud rates ranging from 1 Mbps to 6 bps at 16x
mode at 16 MIPS
• Baud rates ranging from 4 Mbps to 24.4 bps at 4x
mode at 16 MIPS
• 4-deep First-In First-Out (FIFO) Transmit Data
buffer
• 4-deep FIFO Receive Data buffer
• Parity, framing and buffer overrun error detection
• Support for 9-bit mode with Address Detect
(9th bit = 1)
• Transmit and Receive interrupts
• A separate interrupt for all UART error conditions
• Loopback mode for diagnostic support
• Support for sync and break characters
• Support for automatic baud rate detection
• IrDA^® encoder and decoder logic
• 16x baud clock output for IrDA^® support
A simplified block diagram of the UART module is
shown in Figure 18-1. The UART module consists of
these key hardware elements:
• Baud Rate Generator
• Asynchronous Transmitter
• Asynchronous Receiver
FIGURE 18-1:
UART SIMPLIFIED BLOCK DIAGRAM
Baud Rate Generator
IrDA^®
Hardware Flow Control
UART Receiver
UxRTS/BCLK
UxCTS
UxRX
UART Transmitter
UxTX
© 2011-2012 Microchip Technology Inc.
Preliminary
DS39997C-page 185