PIC24FJ16MC101_12 Datasheet, PDF (235/350 Pages) Microchip Technology – 16-bit Microcontrollers (up to 32 KB Flash and 2 KB SRAM)

PIC24FJ16MC101/102 AND PIC24FJ32MC101/102/104
23.0 SPECIAL FEATURES
Note 1: This data sheet summarizes the features
of the PIC24FJ16MC101/102 and
PIC24FJ32MC101/102/104 devices. It is
not intended to be a comprehensive ref-
erence source. To complement the infor-
mation in this data sheet, refer to Section
9. “Watchdog Timer (WDT)” (DS39697)
and Section 33. “Programming and
Diagnostics” (DS39716) in the “PIC24F
Family Reference Manual”, which are
available from the Microchip web site
(www.microchip.com).
2: It is important to note that the
specifications in Section 26.0 “Electri-
cal Characteristics” of this data sheet,
supercede any specifications that may be
provided in PIC24F Family Reference
Manual sections.
3: Some registers and associated bits
described in this section may not be
available on all devices. Refer to
Section 4.0 “Memory Organization” in
this data sheet for device-specific register
and bit information.
PIC24FJ16MC101/102 and PIC24FJ32MC101/102/
104 devices include several features intended to
maximize application flexibility and reliability, and
minimize cost through elimination of external
components. These are:
• Flexible configuration
• Watchdog Timer (WDT)
• Code Protection
• In-Circuit Serial Programming™ (ICSP™)
• In-Circuit emulation
23.1 Configuration Bits
The Configuration Shadow register bits can be config-
ured (read as ‘0’), or left unprogrammed (read as ‘1’),
to select various device configurations. These read-
only bits are mapped starting at program memory loca-
tion 0xF80000. A detailed explanation of the various bit
functions is provided in Table 23-4.
Note that address 0xF80000 is beyond the user pro-
gram memory space and belongs to the configuration
memory space (0x800000-0xFFFFFF) which can only
be accessed using table reads.
In PIC24FJ16MC101/102 and PIC24FJ32MC101/102/
104 devices, the configuration bytes are implemented as
volatile memory. This means that configuration data
must be programmed each time the device is powered
up. Configuration data is stored in the two words at the
top of the on-chip program memory space, known as the
Flash Configuration Words. Their specific locations are
shown in Table 23-2. These are packed representations
of the actual device Configuration bits, whose actual
locations are distributed among several locations in con-
figuration space. The configuration data is automatically
loaded from the Flash Configuration Words to the proper
Configuration registers during device Resets.
Note: Configuration data is reloaded on all types
of device Resets.
When creating applications for these devices, users
should always specifically allocate the location of the
Flash Configuration Word for configuration data. This is
to make certain that program code is not stored in this
address when the code is compiled.
The upper byte of all Flash Configuration Words in pro-
gram memory should always be ‘1111 1111’. This
makes them appear to be NOP instructions in the
remote event that their locations are ever executed by
accident. Since Configuration bits are not implemented
in the corresponding locations, writing ‘1’s to these
locations has no effect on device operation.
Note:
Performing a page erase operation on the
last page of program memory clears the
Flash Configuration Words, enabling code
protection as a result. Therefore, users
should avoid performing page erase
operations on the last page of program
memory.
© 2011-2012 Microchip Technology Inc.
Preliminary
DS39997C-page 235