PIC24FJ16MC101_12 Datasheet, PDF (163/350 Pages) Microchip Technology – 16-bit Microcontrollers (up to 32 KB Flash and 2 KB SRAM)

PIC24FJ16MC101/102 AND PIC24FJ32MC101/102/104
REGISTER 15-6: PWMxCON2: PWM CONTROL REGISTER 2
U-0
—
bit 15
U-0
U-0
U-0
R/W-0
—
—
—
R/W-0
R/W-0
SEVOPS<3:0>
R/W-0
bit 8
U-0
—
bit 7
U-0
U-0
U-0
U-0
R/W-0
R/W-0
R/W-0
—
—
—
—
IUE
OSYNC
UDIS
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 15-12
bit 11-8
bit 7-3
bit 2
bit 1
bit 0
Unimplemented: Read as ‘0’
SEVOPS<3:0>: PWM Special Event Trigger Output Postscale Select bits
1111 = 1:16 postscale
•
•
•
0001 = 1:2 postscale
0000 = 1:1 postscale
Unimplemented: Read as ‘0’
IUE: Immediate Update Enable bit
1 = Updates to the active PxDC registers are immediate
0 = Updates to the active PxDC registers are synchronized to the PWM time base
OSYNC: Output Override Synchronization bit
1 = Output overrides via the PxOVDCON register are synchronized to the PWM time base
0 = Output overrides via the PxOVDCON register occur on next TCY boundary
UDIS: PWM Update Disable bit
1 = Updates from Duty Cycle and Period Buffer registers are disabled
0 = Updates from Duty Cycle and Period Buffer registers are enabled
© 2011-2012 Microchip Technology Inc.
Preliminary
DS39997C-page 163