PIC24FJ16MC101_12 Datasheet, PDF (55/350 Pages) Microchip Technology – 16-bit Microcontrollers (up to 32 KB Flash and 2 KB SRAM)

PIC24FJ16MC101/102 AND PIC24FJ32MC101/102/104
TABLE 4-34: FUNDAMENTAL ADDRESSING MODES SUPPORTED
Addressing Mode
Description
File Register Direct
The address of the file register is specified explicitly.
Register Direct
The contents of a register are accessed directly.
Register Indirect
The contents of Wn forms the Effective Address (EA).
Register Indirect Post-Modified
The contents of Wn forms the EA. Wn is post-modified (incremented
or decremented) by a constant value.
Register Indirect Pre-Modified
Wn is pre-modified (incremented or decremented) by a signed constant value
to form the EA.
Register Indirect with Register Offset The sum of Wn and Wb forms the EA.
(Register Indexed)
Register Indirect with Literal Offset The sum of Wn and a literal forms the EA.
4.3.3 MOVE INSTRUCTIONS
Move instructions provide a greater degree of address-
ing flexibility than other instructions. In addition to the
addressing modes supported by most MCU
instructions, move instructions also support Register
Indirect with Register Offset Addressing mode, also
referred to as Register Indexed mode.
Note:
For the MOV instructions, the addressing
mode specified in the instruction can differ
for the source and destination EA.
However, the 4-bit Wb (Register Offset)
field is shared by both source and
destination (but typically only used by
one).
In summary, the following addressing modes are
supported by move instructions:
• Register Direct
• Register Indirect
• Register Indirect Post-modified
• Register Indirect Pre-modified
• Register Indirect with Register Offset (Indexed)
• Register Indirect with Literal Offset
• 8-bit Literal
• 16-bit Literal
Note:
Not all instructions support all the
addressing modes given above. Individual
instructions may support different subsets
of these addressing modes.
4.3.4 OTHER INSTRUCTIONS
In addition to the addressing modes outlined previously,
some instructions use literal constants of various sizes.
For example, BRA (branch) instructions use 16-bit signed
literals to specify the branch destination directly, whereas
the DISI instruction uses a 14-bit unsigned literal field. In
some instructions, such as ADD Acc, the source of an
operand or result is implied by the opcode itself. Certain
operations, such as NOP, do not have any operands.
4.4 Interfacing Program and Data
Memory Spaces
The PIC24FJ16MC101/102 and PIC24FJ32MC101/
102/104 architecture uses a 24-bit-wide program space
and a 16-bit-wide data space. The architecture is also
a modified Harvard scheme, meaning that data can
also be present in the program space. To use this data
successfully, it must be accessed in a way that pre-
serves the alignment of information in both spaces.
Aside from normal execution, the PIC24FJ16MC101/
102 and PIC24FJ32MC101/102/104 architecture
provides two methods by which program space can be
accessed during operation:
• Using table instructions to access individual
bytes, or words, anywhere in the program space
• Remapping a portion of the program space into
the data space (Program Space Visibility)
Table instructions allow an application to read or write
to small areas of the program memory. This capability
makes the method ideal for accessing data tables that
need to be updated periodically. It also allows access
to all bytes of the program word. The remapping
method allows an application to access a large block of
data on a read-only basis, which is ideal for lookups
from a large table of static data. The application can
only access the lsw of the program word.
4.4.1 ADDRESSING PROGRAM SPACE
Since the address ranges for the data and program
spaces are 16 and 24 bits, respectively, a method is
needed to create a 23-bit or 24-bit program address
from 16-bit data registers. The solution depends on the
interface method to be used.
For table operations, the 8-bit Table Page register
(TBLPAG) is used to define a 32K word region within the
program space. This is concatenated with a 16-bit EA to
arrive at a full 24-bit program space address. In this for-
mat, the MSb of TBLPAG is used to determine if the
operation occurs in the user memory (TBLPAG<7> = 0)
or the configuration memory (TBLPAG<7> = 1).
© 2011-2012 Microchip Technology Inc.
Preliminary
DS39997C-page 55