PIC24FJ16MC101_12 Datasheet, PDF (141/350 Pages) Microchip Technology – 16-bit Microcontrollers (up to 32 KB Flash and 2 KB SRAM)

PIC24FJ16MC101/102 AND PIC24FJ32MC101/102/104
12.0 TIMER2/3 FEATURE
Note 1: This data sheet summarizes the features
of the PIC24FJ16MC101/102 and
PIC24FJ32MC101/102/104 family of
devices. It is not intended to be a
comprehensive reference source. To
complement the information in this data
sheet, refer to Section 14. “Timers”
(DS39704) in the “PIC24F Family
Reference Manual”, which is available
from the Microchip web site
(www.microchip.com).
2: It is important to note that the
specifications in Section 26.0 “Electri-
cal Characteristics” of this data sheet,
supercede any specifications that may be
provided in PIC24F Family Reference
Manual sections.
3: Some registers and associated bits
described in this section may not be
available on all devices. Refer to
Section 4.0 “Memory Organization” in
this data sheet for device-specific register
and bit information.
Timer2/3 and Timer4/5 have three 2-bit timers that can
also be configured as two independent 16-bit timers
with selectable operating modes.
Note 1: Timer4 and Timer5 are available in
PIC24FJ32MC10X) devices only.
As a 32-bit timer, Timer2/3 and Timer4/5 permit
operation in three modes:
• Two Independent 16-bit timers (e.g., Timer2 and
Timer3 or Timer4 and Timer5) with all 16-bit
operating modes (except Asynchronous Counter
mode)
• Single 32-bit timer (Timer2/3 and Timer4/5)
• Single 32-bit synchronous counter (Timer2/3 and
Timer4/5)
Timer2/3 and Timer4/5 also support:
• Timer gate operation
• Selectable prescaler settings
• Timer operation during Idle and Sleep modes
• Interrupt on a 32-bit period register match
• Time base for Input Capture and Output Compare
modules (Timer2 and Timer3 only)
• ADC1 event trigger (Timer2/3 only)
Individually, all eight of the 16-bit timers can function as
synchronous timers or counters. They also offer the
features listed above, except for the event trigger. The
operating modes and enabled features are determined
by setting the appropriate bit(s) in the T2CON, T3CON,
T4CON, and T5CON registers (see Register 12-1
through Register 12-2).
For 32-bit timer/counter operation, Timer2/4 is the least
significant word (lsw), and Timer3/5 is the most
significant word (msw) of the 32-bit timers.
Note:
For 32-bit operation, T3CON and T5CON
control bits are ignored. Only T2CON and
T4CON control bits are used for setup and
control. Timer2 and Timer4 clock and gate
inputs are used for the 32-bit timer
modules, but an interrupt is generated
with the Timer3 and Timer5 interrupt flags.
12.1 32-bit Operation
To configure Timer2/3 and Timer4/5 for 32-bit
operation:
1. Set the T32 control bit.
2. Select the prescaler ratio for Timer2 or Timer4
using the TCKPS<1:0> bits.
3. Set the Clock and Gating modes using the
corresponding TCS and TGATE bits.
4. Load the timer period value. PR3/PR5 contains
the msw of the value, while PR2/PR4 contains
the least significant word (lsw).
5. If interrupts are required, set the interrupt enable
bit, T3IE or T5IE. Use the priority bits,
T3IP<2:0> or T5IP<2:0>, to set the interrupt pri-
ority. While Timer2/Timer4 controls the timer, the
interrupt appears as a Timer3/Timer5 interrupt.
6. Set the corresponding TON bit.
The timer value at any point is stored in the register
pair, TMR3:TMR2 or TMR5:TMR4, which always
contains the msw of the count, while TMR2 or TMR4
contains the lsw.
12.2 16-bit Operation
To configure any of the timers for individual 16-bit
operation:
1. Clear the T32 bit corresponding to that timer.
2. Select the timer prescaler ratio using the
TCKPS<1:0> bits.
3. Set the Clock and Gating modes using the TCS
and TGATE bits.
4. Load the timer period value into the PRx
register.
5. If interrupts are required, set the interrupt enable
bit, TxIE. Use the priority bits, TxIP<2:0>, to set
the interrupt priority.
6. Set the TON bit.
© 2011-2012 Microchip Technology Inc.
Preliminary
DS39997C-page 141