PIC24FJ16MC101_12 Datasheet, PDF (56/350 Pages) Microchip Technology – 16-bit Microcontrollers (up to 32 KB Flash and 2 KB SRAM)

PIC24FJ16MC101/102 AND PIC24FJ32MC101/102/104
For remapping operations, the 8-bit Program Space
Visibility register (PSVPAG) is used to define a
16K word page in the program space. When the MSb
of the EA is ‘1’, PSVPAG is concatenated with the lower
15 bits of the EA to form a 23-bit program space
address. Unlike table operations, this limits remapping
operations strictly to the user memory area.
Table 4-35 and Figure 4-7 show how the program EA is
created for table operations and remapping accesses
from the data EA.
TABLE 4-35: PROGRAM SPACE ADDRESS CONSTRUCTION
Access Type
Access
Space
Program Space Address
<23>
<22:16>
<15>
<14:1>
<0>
Instruction Access
(Code Execution)
User
0
PC<22:1>
0
0xx xxxx xxxx xxxx xxxx xxx0
TBLRD/TBLWT
User
(Byte/Word Read/Write)
TBLPAG<7:0>
0xxx xxxx
Data EA<15:0>
xxxx xxxx xxxx xxxx
Configuration
TBLPAG<7:0>
Data EA<15:0>
Program Space Visibility User
(Block Remap/Read)
1xxx xxxx
xxxx xxxx xxxx xxxx
0
PSVPAG<7:0>
Data EA<14:0>⁽¹⁾
0
xxxx xxxx
xxx xxxx xxxx xxxx
Note 1: Data EA<15> is always ‘1’ in this case, but is not used in calculating the program space address. Bit 15 of
the address is PSVPAG<0>.
FIGURE 4-7:
DATA ACCESS FROM PROGRAM SPACE ADDRESS GENERATION
Program Counter⁽¹⁾
0
Program Counter
0
23 bits
Table Operations⁽²⁾
1/0
TBLPAG
8 bits
EA
1/0
16 bits
24 bits
Select
1
EA
0
Program Space Visibility⁽¹⁾
(Remapping)
0
PSVPAG
8 bits
15 bits
23 bits
User/Configuration Space Select
Byte Select
Note 1: The Least Significant bit of program space addresses is always fixed as ‘0’ to maintain word alignment
of data in the program and data spaces.
2: Table operations are not required to be word aligned. Table read operations are permitted in the
Configuration memory space.
DS39997C-page 56
Preliminary
© 2011-2012 Microchip Technology Inc.