PIC24FJ16MC101_12 Datasheet, PDF (171/350 Pages) Microchip Technology – 16-bit Microcontrollers (up to 32 KB Flash and 2 KB SRAM)

PIC24FJ16MC101/102 AND PIC24FJ32MC101/102/104
16.0 SERIAL PERIPHERAL
INTERFACE (SPI)
Note 1: This data sheet summarizes the features
of the PIC24FJ16MC101/102 and
PIC24FJ32MC101/102/104 family of
devices. It is not intended to be a
comprehensive reference source. To
complement the information in this data
sheet, refer to Section 23. “Serial
Peripheral Interface (SPI)” (DS39699)
in the “PIC24F Family Reference
Manual”, which is available from the
Microchip
web
site
(www.microchip.com).
2: It is important to note that the
specifications in Section 26.0 “Electri-
cal Characteristics” of this data sheet,
supercede any specifications that may be
provided in PIC24F Family Reference
Manual sections.
3: Some registers and associated bits
described in this section may not be
available on all devices. Refer to
Section 4.0 “Memory Organization” in
this data sheet for device-specific register
and bit information.
The Serial Peripheral Interface (SPI) module is a syn-
chronous serial interface useful for communicating with
other peripheral or microcontroller devices. These
peripheral devices can be serial EEPROMs, shift regis-
ters, display drivers, analog-to-digital converters, etc.
The SPI module is compatible with SPI and SIOP from
Motorola^®.
Each SPI module consists of a 16-bit shift register,
SPIxSR (where x = 1 or 2), used for shifting data in and
out, and a buffer register, SPIxBUF. A control register,
SPIxCON, configures the module. Additionally, a status
register, SPIxSTAT, indicates status conditions.
The serial interface consists of four pins:
• SDIx (serial data input)
• SDOx (serial data output)
• SCKx (shift clock input or output)
• SSx (active low slave select).
In Master mode operation, SCK is a clock output. In
Slave mode, it is a clock input.
FIGURE 16-1:
SPI MODULE BLOCK DIAGRAM
SCKx
SSx
SDOx
SDIx
Sync
Control
Control
Clock
Select
Edge
Shift Control
bit 0
SPIxSR
1:1 to 1:8
Secondary
Prescaler
1:1/4/16/64
Primary
FCY
Prescaler
SPIxCON1<1:0>
SPIxCON1<4:2>
Enable
Master Clock
Transfer
Transfer
SPIxRXB SPIxTXB
SPIxBUF
Read SPIxBUF
Write SPIxBUF
16
Internal Data Bus
© 2011-2012 Microchip Technology Inc.
Preliminary
DS39997C-page 171