PIC24FJ16MC101_12 Datasheet, PDF(119/350 Page) Microchip Technology – 16-bit Microcontrollers (up to 32 KB Flash and 2 KB SRAM)

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PIC24FJ16MC101_12 Datasheet, PDF (119/350 Pages) Microchip Technology – 16-bit Microcontrollers (up to 32 KB Flash and 2 KB SRAM)

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PIC24FJ16MC101/102 AND PIC24FJ32MC101/102/104

TABLE 10-2: OUTPUT SELECTION FOR REMAPPABLE PIN (RPn)

Function

RPnR<4:0>

Output Name

NULL

C1OUT

C2OUT

U1TX

00000

00001

00010

00011

RPn tied to default port pin

RPn tied to Comparator 1 Output

RPn tied to Comparator 2 Output

RPn tied to UART1 Transmit

U1RTS

SCK1

SDO1

00100

01000

00111

RPn tied to UART1 Ready To Send

RPn tied to SPI Clock(1)

RPn tied to SPI Data Output(1)

SS1

01001

RPn tied to SPI1 Slave Select Output

OC1

10010

RPn tied to Output Compare 1

OC2

10011

RPn tied to Output Compare 2

CTPLS

11101

RPn tied to CTMU Pulse Output

C3OUT

11110

RPn tied to Comparator 3 Output

Note 1: This function is available in PIC24FJ32MC101/102/104 devices only.

10.4.3 CONTROLLING CONFIGURATION

CHANGES

Because peripheral remapping can be changed during

run time, some restrictions on peripheral remapping are

needed to prevent accidental configuration changes.

PIC24FJ16MC101/102 and PIC24FJ32MC101/102/104

devices include three features to prevent alterations to

the peripheral map:

â¢ Control register lock sequence

â¢ Continuous state monitoring

â¢ Configuration bit pin select lock

10.4.3.1 Control Register Lock Sequence

Under normal operation, writes to the RPINRx and

RPORx registers are not allowed. Attempted writes

appear to execute normally, but the contents of the

registers remain unchanged. To change these

registers, they must be unlocked in hardware. The

register lock is controlled by the IOLOCK bit

(OSCCON<6>). Setting IOLOCK prevents writes to the

control registers; clearing IOLOCK allows writes.

To set or clear IOLOCK, a specific command sequence

must be executed:

1. Write 0x46 to OSCCON<7:0>.

2. Write 0x57 to OSCCON<7:0>.

3. Clear (or set) IOLOCK as a single operation.

Note:

MPLABÂ® C30 provides built-in C

language functions for unlocking the

OSCCON register:

__builtin_write_OSCCONL(value)

__builtin_write_OSCCONH(value)

See MPLAB IDE Help for more

information.

Unlike the similar sequence with the oscillatorâs LOCK

bit, IOLOCK remains in one state until changed. This

allows all of the peripheral pin selects to be configured

with a single unlock sequence followed by an update to

all control registers, then locked with a second lock

sequence.

10.4.3.2 Continuous State Monitoring

In addition to being protected from direct writes, the

contents of the RPINRx and RPORx registers are

constantly monitored in hardware by shadow registers.

If an unexpected change in any of the registers occurs

(such as cell disturbances caused by ESD or other

external events), a configuration mismatch Reset will

be triggered.

10.4.3.3 Configuration Bit Pin Select Lock

As an additional level of safety, the device can be

configured to prevent more than one write session to

the RPINRx and RPORx registers. The IOL1WAY

(FOSC<IOL1WAY>) configuration bit blocks the

IOLOCK bit from being cleared after it has been set

once. If IOLOCK remains set, the register unlock

procedure will not execute, and the peripheral pin

select control registers cannot be written to. The only

way to clear the bit and re-enable peripheral remapping

is to perform a device Reset.

In the default (unprogrammed) state, IOL1WAY is set,

restricting users to one write session. Programming

IOL1WAY allows user applications unlimited access

(with the proper use of the unlock sequence) to the

peripheral pin select registers.

Â© 2011-2012 Microchip Technology Inc.

Preliminary

DS39997C-page 119

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