PIC24FJ16MC101_12 Datasheet, PDF (106/350 Pages) Microchip Technology – 16-bit Microcontrollers (up to 32 KB Flash and 2 KB SRAM)

PIC24FJ16MC101/102 AND PIC24FJ32MC101/102/104
REGISTER 8-2: CLKDIV: CLOCK DIVISOR REGISTER
R/W-0
ROI
bit 15
R/W-0
R/W-1
R/W-1
DOZE<2:0>^(2,3)
R/W-0
DOZEN^(1,2,3)
R/W-0
R/W-0
FRCDIV<2:0>
R/W-0
bit 8
U-0
—
bit 7
U-0
U-0
U-0
U-0
—
—
—
—
U-0
U-0
U-0
—
—
—
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 15
bit 14-12
bit 11
bit 10-8
bit 7-0
ROI: Recover on Interrupt bit
1 = Interrupts will clear the DOZEN bit and the processor clock/peripheral clock ratio is set to 1:1
0 = Interrupts have no effect on the DOZEN bit
DOZE<2:0>: Processor Clock Reduction Select bits^(2,3)
111 = FCY/128
110 = FCY/64
101 = FCY/32
100 = FCY/16
011 = FCY/8 (default)
010 = FCY/4
001 = FCY/2
000 = FCY/1
DOZEN: DOZE Mode Enable bit^(1,2,3)
1 = DOZE<2:0> field specifies the ratio between the peripheral clocks and the processor clocks
0 = Processor clock/peripheral clock ratio forced to 1:1
FRCDIV<2:0>: Internal Fast RC Oscillator Postscaler bits
111 = FRC divide by 256
110 = FRC divide by 64
101 = FRC divide by 32
100 = FRC divide by 16
011 = FRC divide by 8
010 = FRC divide by 4
001 = FRC divide by 2
000 = FRC divide by 1 (default)
Unimplemented: Read as ‘0’
Note 1:
2:
3:
This bit is cleared when the ROI bit is set and an interrupt occurs.
If DOZEN = 1, writes to DOZE<2:0> are ignored.
If DOZE<2:0> = 000, the DOZEN bit cannot be set by the user; writes are ignored.
DS39997C-page 106
Preliminary
© 2011-2012 Microchip Technology Inc.