PIC24FJ16MC101_12 Datasheet, PDF (115/350 Pages) Microchip Technology – 16-bit Microcontrollers (up to 32 KB Flash and 2 KB SRAM)

PIC24FJ16MC101/102 AND PIC24FJ32MC101/102/104
10.0 I/O PORTS
Note 1: This data sheet summarizes the features of
the
PIC24FJ16MC101/102
and
PIC24FJ32MC101/102/104 family of
devices. It is not intended to be a
comprehensive reference source. To com-
plement the information in this data
sheet, refer to Section 12. “I/O Ports with
Peripheral Pin Select (PPS)” (DS39711)
in the “PIC24F Family Reference Man-
ual”, which is available from the
Microchip web site (www.microchip.com).
2: It is important to note that the
specifications in Section 26.0 “Electri-
cal Characteristics” of this data sheet,
supercede any specifications that may be
provided in PIC24F Family Reference
Manual sections.
3: Some registers and associated bits
described in this section may not be
available on all devices. Refer to
Section 4.0 “Memory Organization” in
this data sheet for device-specific register
and bit information.
All of the device pins (except VDD, VSS, MCLR, and
OSC1/CLKI) are shared among the peripherals and the
parallel I/O ports. All I/O input ports feature Schmitt
Trigger inputs for improved noise immunity.
10.1 Parallel I/O (PIO) Ports
Generally a parallel I/O port that shares a pin with a
peripheral is subservient to the peripheral. The
peripheral’s output buffer data and control signals are
provided to a pair of multiplexers. The multiplexers
select whether the peripheral or the associated port
has ownership of the output data and control signals of
the I/O pin. The logic also prevents “loop through,” in
which a port’s digital output can drive the input of a
peripheral that shares the same pin. Figure 10-1 shows
how ports are shared with other peripherals and the
associated I/O pin to which they are connected.
When a peripheral is enabled and the peripheral is
actively driving an associated pin, the use of the pin as
a general purpose output pin is disabled. The I/O pin
can be read, but the output driver for the parallel port bit
is disabled. If a peripheral is enabled, but the peripheral
is not actively driving a pin, that pin can be driven by a
port.
All port pins have three registers directly associated
with their operation as digital I/O. The data direction
register (TRISx) determines whether the pin is an input
or an output. If the data direction bit is a ‘1’, the pin is
an input. All port pins are defined as inputs after a
Reset. Reads from the latch (LATx) read the latch.
Writes to the latch write the latch. Reads from the port
(PORTx) read the port pins, while writes to the port pins
write the latch.
Any bit and its associated data and control registers
that are not valid for a particular device will be
disabled. This means the corresponding LATx and
TRISx registers and the port pin will read as zeros.
When a pin is shared with another peripheral or
function that is defined as an input only, it is
nevertheless regarded as a dedicated port because
there is no other competing source of outputs.
FIGURE 10-1:
BLOCK DIAGRAM OF A TYPICAL SHARED PORT STRUCTURE
Peripheral Module
Peripheral Input Data
Peripheral Module Enable
Peripheral Output Enable
Peripheral Output Data
Read TRIS
PIO Module
Output Multiplexers
I/O
1
Output Enable
0
1
Output Data
0
Data Bus
WR TRIS
WR LAT +
WR Port
Read LAT
Read Port
DQ
CK
TRIS Latch
D
Q
CK
Data Latch
I/O Pin
Input Data
© 2011-2012 Microchip Technology Inc.
Preliminary
DS39997C-page 115