JG82855GMESL7VN Datasheet, PDF (98/213 Pages) Intel Corporation – Intel® 855GM/855GME Chipset Graphics and Memory Controller Hub (GMCH)

Register Description
R
4.9.15
PWRMG – DRAM Controller Power Management Control
Register (Device #0)
Address Offset:
Default Value:
Access:
Size:
68h-6Bh
00000000h
Read/Write
32 bits
Bit
31:24
23:20
Description
Reserved
Row State Control: This field determines the number of clocks the System Memory Controller will
remain in the idle state before it begins pre-charging all pages or powering down rows.
- PDEn: Power Down Enable
- PCEn: Page Close Enable
- TC: Timer Control
19:16
15
14
13
12
PDEn(23): PCEn(22): TC(21:20)
Function
0
0
XX
All Disabled
0
1
XX
Reserved
1
0
XX
Reserved
1
1
00
Immediate Precharge and Powerdown
1
1
01
Reserved
1
1
10
Precharge and Power Down after 16 DDR SDRAM Clocks
1
1
11
Precharge and Power Down after 64 DDR SDRAM Clocks
Reserved
Self Refresh GMCH Memory Interface Data Bus Power Management Optimization Enable:
0 = Enable
1 = Disable
CS# Signal Drive Control:
0 = Enable CS# Drive Control, based on rules described in DRC bit 12.
1 = Disable CS# Drive Control, based on rules described in DRC bit 12.
Self Refresh GMCH Memory Interface Data Bus Power Management:
0 = In Self Refresh Mode GMCH Power Management is Enabled.
1 = In Self Refresh Mode the GMCH Power Management is Disabled.
Dynamic Memory Interface Power Management:
0 = Dynamic Memory Interface Power Management Enabled.
1 = Dynamic Memory Interface Power Management Disabled.
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Datasheet