JG82855GMESL7VN Datasheet, PDF (104/213 Pages) Intel Corporation – Intel® 855GM/855GME Chipset Graphics and Memory Controller Hub (GMCH)

Register Description
R
104
Bit
19:16
15:12
11
10
9
Description
Read Thermal Based Power Throttle Control (RTTC): These bits select the Thermal Sensor based
Power Throttle Bandwidth Limits for Read operations to system memory.
R/W, RO if Throttle Lock.
0h = 85%
1h = 70%
2h = 65%
3h = 60%
4h = 55%
5h = 50%
6h = 45%
7h = 40%
8h = 35%
9h = 30%
Ah = 20%
B-Fh = Reserved
Write Thermal Based Power Throttle Control (WTTC): These bits select the Thermal based Power
Throttle Bandwidth Limits for Write operations to system memory.
R/W, RO if Throttle Lock
0h = 85%
1h = 70%
2h = 65%
3h = 60%
4h = 55%
5h = 50%
6h = 45%
7h = 40%
8h = 35%
9h = 30%
Ah = 20%
B-Fh = Reserved
Counter Based Throttle Lock (CTLOCK): This bit secures RCTC and WCTC. This bit defaults to 0.
Once a 1 is written to this bit, RCTC and WCTC (including CTLOCK) become Read-Only.
Thermal Throttle Lock (TTLOCK): This bit secures the DDR SDRAM Throttling Control register. This
bit defaults to 0. Once a 1 is written to this bit, all of the configuration register bits in DTC (including
TTLOCK) except CTLOCK, RCTC and WCTC become Read-Only.
Thermal Power Throttle Control fields Enable:
0 = RTTC and WTTC are not used. RCTC and WTCT are used for both Counter and Thermal based
Throttling.
1 = RTTC and WTTC are used for Thermal based Throttling.
Datasheet