JG82855GMESL7VN Datasheet, PDF (161/213 Pages) Intel Corporation – Intel® 855GM/855GME Chipset Graphics and Memory Controller Hub (GMCH)

Functional Description
R
Table 41. PCI Commands Supported by the GMCH When Acting as a FRAME# Target
PCI Command
C/BE[3:0]# Encoding
Interrupt Acknowledge
Special Cycle
I/O Read
I/O Write
Reserved
Reserved
Memory Read
Memory Write
Reserved
Reserved
Configuration Read
Configuration Write
Memory Read Multiple
Dual Address Cycle
Memory Read Line
Memory Write and
Invalidate
0000
0001
0010
0011
0100
0101
0110
0110
0111
0111
1000
1001
1010
1011
1100
1100
1101
1110
1110
1111
1111
NOTE: N/A refers to a function that is not applicable.
GMCH
Cycle Destination
Response as A FRAME#
Target
N/A
N/A
N/A
N/A
N/A
N/A
Main Memory
The Hub interface
Main Memory
The Hub interface
N/A
N/A
N/A
N/A
Main Memory
The Hub interface
N/A
Main Memory
The Hub interface
Main Memory
No Response
No Response
No Response
No Response
No Response
No Response
Read
No Response
Posts Data
No Response
No Response
No Response
No Response
No Response
Read
No Response
No Response
Read
No Response
Posts Data
The Hub interface
No Response
As a target of an AGP FRAME# cycle, the GMCH only supports the following transactions:
• Memory Read, Memory Read Line, and Memory Read Multiple. These commands are
supported identically by the GMCH. The GMCH does not support reads of the hub interface
bus from AGP.
• Memory Write and Memory Write and Invalidate. These commands are aliased and
processed identically. The GMCH does not support writes to the hub interface bus from
AGP.
• Other Commands. Other commands such as I/O R/W and Configuration R/W are not
supported by the GMCH as a target and result in master abort.
• Exclusive Access. The GMCH does not support PCI locked cycles as a target.
Datasheet
161