JG82855GMESL7VN Datasheet, PDF (134/213 Pages) Intel Corporation – Intel® 855GM/855GME Chipset Graphics and Memory Controller Hub (GMCH)

Intel® 855GM/GME GMCH System Address Map
R
5.4.7.2
target device (DDR SDRAM) will complete normally. The remaining portion of the access that
crosses a device boundary (targets a different device than that of the starting address) or hits an
invalid address will be remapped to system memory address 0h, snooped on the Host Bus, and
dispatched to DDR SDRAM. Reads will return all 1’s with Master Abort completion. Writes will
have BE’s (Byte Enable) deasserted and will terminate with Master Abort if completion is
required.
If the starting address of a transaction hits an invalid address the entire transaction will be
remapped to system memory address 0h, snooped on the Host Bus, and dispatched to DDR
SDRAM. Reads will return all 1’s with Master Abort completion. Writes will have BE’s
deasserted and will terminate with Master Abort if completion is required.
AGP Interface Decode Rules
Cycles Initiated Using PCI Protocol
The GMCH does not support any AGP/PCI access targeting Hub interface. The GMCH will claim
AGP/PCI initiated memory read and write transactions decoded to the main DDR SDRAM range
or the Graphics Aperture range. All other memory read and write requests will be master-aborted
by the AGP/PCI initiator as a consequence of GMCH not responding to a transaction.
Under certain conditions, the GMCH restrict access to the DOS Compatibility ranges governed by
the PAM registers by distinguishing access type and destination bus. The GMCH accept
AGP/PCI write transactions to the compatibility ranges if the PAM designates DDR SDRAM as
write-able. If accesses to a range are not write enabled by the PAM, the GMCH does not respond
and the cycle will result in a master-abort. The GMCH accept AGP/PCI read transactions to the
compatibility ranges if the PAM designates DDR SDRAM as readable. If accesses to a range are
not read enabled by the PAM, the GMCH does not respond and the cycle will result in a master-
abort.
If agent on AGP/PCI issues an I/O or PCI Special Cycle transaction, the GMCH will not respond
and cycle will result in a master-abort. The GMCH will accept PCI configuration cycles to the
internal GMCH devices as part of the PCI configuration/co-pilot mode mechanism.
Cycles Initiated Using AGP Protocol
All cycles must reference main memory i.e. main DDR SDRAM address range (excluding PAM)
or Graphics Aperture range (also physically mapped within DDR SDRAM but using different
address range). AGP accesses to the PAM region from 640K -to- 1M are not allowed. AGP
accesses to SMM space are not allowed. AGP initiated cycles that target DDR SDRAM are not
snooped on the host bus, even if they fall outside of the AGP aperture range.
If a cycle is outside of a valid main memory range then it will terminate as follows:
• Reads: Remap to memory address 0h, return data from address 0h, and set the IAAF error
flag.
• Writes:Remapped to memory address 0h with BE’s de-asserted (effectively dropped “on the
floor”) and set the IAAF error flag.
AGP Accesses to GMCH that Cross Device Boundaries
For FRAME# accesses, when an AGP or PCI master gets disconnected it will resume at the new
address which allows the cycle to be routed to or claimed by the new target. Therefore accesses
134
Datasheet