JG82855GMESL7VN Datasheet, PDF (81/213 Pages) Intel Corporation – Intel® 855GM/855GME Chipset Graphics and Memory Controller Hub (GMCH)

Register Description
R
4.8.27
AGPCMD – AGP Command Register (Device #0)
Address Offset:
Default Value:
Access:
Size:
A8–ABh
00000000h
Read/Write
32 bits
This register provides control of the AGP operational parameters.
Bit
31:10
9
8
7:6
5
4
3
2:0
Description
Reserved
Side Band Addressing Enable (SBA_EN). When this bit is set to 1, the side band addressing
mechanism is enabled.
AGP Enable.
0 = Disable. When this bit is reset to 0, the GMCH will ignore all AGP operations, including the sync
cycle. Any AGP operations received while this bit is set to 1 will be serviced even if this bit is reset
to 0. If this bit transitions from a 1 to a 0 on a clock edge in the middle of an SBA command being
delivered in 1X mode, the command will be issued.
1 = Enable. The GMCH will respond to AGP operations delivered via PIPE#, or to operations
delivered via SBA if the AGP Side Band Enable bit is also set to 1.
Reserved
Address Support Above 4 GB Enable (4 GB_EN). The GMCH as an AGP target does not support
addressing greater than 4 gigabytes.
Fast Write Enable.
1 = Enable. GMCH AGP master supports Fast Writes.
0 = Disable (Default). Fast Writes are disabled.
Reserved
Data Rate. The settings of these bits determine the AGP data transfer rate. One (and only one) bit in
this field must be set to indicate the desired data transfer rate. Bit 0: 1X, Bit 1: 2X, Bit 2: 4X. The same
bit must be set on both master and target.
Configuration software will update this field by setting only one bit that corresponds to the capability of
AGP master (after that capability has been verified by accessing the same functional register within the
AGP masters configuration space.)
NOTE: The selected data transfer mode applies to both AD bus and SBA bus.
Datasheet
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