JG82855GMESL7VN Datasheet, PDF (131/213 Pages) Intel Corporation – Intel® 855GM/855GME Chipset Graphics and Memory Controller Hub (GMCH)

Intel® 855GM/GME GMCH System Address Map
R
• Above 1-MB option that allows new SMI handlers to execute with Write-back cacheable
SMRAM.
• Above 1-MB solutions require changes to compatible SMRAM handlers code to properly
execute above 1 MB.
Note: Hub interface is not allowed to access the SMM space.
5.4.3.1
SMM Space Restrictions
If any of the following conditions are violated the results of SMM accesses are unpredictable and
may cause the system to hang:
• The Compatible SMM space must not be set-up as cacheable.
• High or TSEG SMM transaction address space must not overlap address space assigned to
DDR SDRAM or to any PCI devices (including Hub interface and graphics devices). This is
a BIOS responsibility.
• Both D_OPEN and D_CLOSE must not be set to 1 at the same time.
When TSEG SMM space is enabled, the TSEG space must not be reported to the OS as available.
This is a BIOS responsibility.
5.4.3.2 SMM Space Definition
SMM space is defined by its addressed SMM space and its DDR SDRAM SMM space. The
addressed SMM space is defined as the range of bus addresses used by the CPU to access SMM
space. DDR SDRAM SMM space is defined as the range of physical DDR SDRAM locations
containing the SMM code. SMM space can be accessed at one of three transaction address ranges:
Compatible, High, and TSEG. The Compatible and TSEG SMM space is not remapped and
therefore the addressed and DDR SDRAM SMM space is the same address range. Since the High
SMM space is remapped the addressed and DDR SDRAM SMM space is a different address
range. Note that the High DDR SDRAM space is the same as the Compatible Transaction
Address space Table 34 describes three unique address ranges:
1. Compatible Transaction Address (Adr C)
2. High Transaction Address (Adr H)
3. TSEG Transaction Address (Adr T)
These abbreviations are used later in Table 34.
Table 34. SMM Space Transaction Handling
SMM Space Enabled
Compatible (C)
High (H)
TSEG (T)
Transaction Address Space (Adr)
A0000h to BFFFFh
0FEDA0000h to 0FEDBFFFFh
(TOM-TSEG_SZ) to TOM
DRAM Space (DRAM)
A0000h to BFFFFh
A0000h to BFFFFh
(TOM-TSEG_SZ) to TOM
Datasheet
131