JG82855GMESL7VN Datasheet, PDF (155/213 Pages) Intel Corporation – Intel® 855GM/855GME Chipset Graphics and Memory Controller Hub (GMCH)

Functional Description
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LVDS Interface Signals
LVDS for flat panel is compatible with the ANSI/TIA/EIA-644 specification. This is an electrical
standard only defining driver output characteristics and receiver input characteristics. There are
two LVDS transmitter channels (channel A and channel B) in the LVDS interface. Each channel
consists of four data pairs and a clock pair. The interface consists of a total of ten differential
signal pairs of which eight are data and two are clocks. The phase locked transmit clock is
transmitted in parallel with the data being sent out over the data pairs and over the LVDS clock
pair.
Each channel supports transmit clock frequency ranges from 35 MHz to 112 MHz, which
provides a throughput of up to 784 Mbps on each data output and up to 112 MHz on the input.
When using both channels, they each operate at the same frequency each carrying a portion of the
data. The maximum pixel rate is increased to 224 MHz but may be limited to less than that due to
restrictions elsewhere in the circuit.
The LVDS Port Enable bit enables or disables the entire LVDS interface. When the port is
disabled, it will be in a low power state. Once the port is enabled, individual driver pairs will be
disabled based on the operating mode. Disabled drivers can be powered down for reduced power
consumption or optionally fixed to forced 0’s output.
LVDS Pair States
The LVDS pairs can be put into one of the following five states: powered down tri-state, powered
down Zero Volts, common mode, send zeros, or active. When in the active state, several data
formats are supported. When in powered down state, the circuit enters a low power state and
drives out 0 V or tri-states on both the output pins for the entire channel. The common mode tri-
state is both pins of the pair set to the common mode voltage. When in the send zeros state, the
circuit is powered up but sends only zero for the pixel color data regardless what the actual data is
with the clock lines and timing signals sending the normal clock and timing data.
Single Channel versus Dual Channel Mode
Both single channel and dual channel modes are available to allow interfacing to either single or
dual channel panel interfaces. This LVDS port can operate in single channel or dual channel
mode. Dual channel mode uses twice the number of LVDS pairs and transfers the pixel data at
twice the rate of the single channel. In general, one channel will be used for even pixels and the
other for odd pixel data. The first pixel of the line is determined by the display enable going
active and that pixel will be sent out channel A. All horizontal timings for active, sync, and blank
will be limited to be on two pixel boundaries in the two channel modes.
LVDS Channel Skew
When in dual channel mode, the two channels must meet the panel requirements with respect to
the inter channel skew.
SSC Support
The GMCH is designed to tolerate 0.5%, 1.0%, and 2.5% down/center spread at a modulation rate
from 30-50 kHz triangle. An external SSC clock synthesizer can be used to provide the
48/66 MHz reference clock into the GMCH Pipe B PLL.
Datasheet
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