JG82855GMESL7VN Datasheet, PDF (100/213 Pages) Intel Corporation – Intel® 855GM/855GME Chipset Graphics and Memory Controller Hub (GMCH)

Register Description
R
Bit
19:16
15
14:13
12
11:10
9:7
6:4
Description
Reserved
RAS Lock-Out Enable: Set to a 1 if all populated rows support RAS Lock-Out. Defaults to 0.
If this bit is set to a 1 the DDR SDRAM Controller assumes that the DDR SDRAM guarantees tRAS min
before an auto precharge (AP) completes (Note: An AP is sent with a Read or a Write command). Also,
the DDR SDRAM Controller does not issue an activate command to the auto pre-charged bank for tRP.
If this bit is set to a 0 the DDR SDRAM Controller does not schedule an AP if tRAS min is not met.
Reserved
Address Tri-state enable (ADRTRIEN): When set to a 1, the SDRAM Controller will tri-state the MA,
CMD, and CS# (only when all CKEs are deasserted). Note that when CKE to a row is deasserted, fast
chip select assertion is not permitted by the hardware. CKEs deassert based on Idle Timer and/or max
row count control.
0:- Address Tri-state Disabled
1:- Address Tri-state Enabled
Reserved
Refresh Mode Select (RMS): This field determines whether Refresh is enabled and, if so, at what rate
Refreshes will be executed.
000: Refresh disabled
001: Refresh enabled. Refresh interval 15.6 µsec
010: Refresh enabled. Refresh interval 7.8 µsec
011: Reserved.
111: Refresh enabled. Refresh interval 64 clocks (fast refresh mode)
Other: Reserved
Any change in the programming of this field Resets the Refresh counter to zero. This function is for
testing purposes, it allows test program to align refresh events with the test and thus improve failure
repeatability.
Mode Select (SMS). These bits select the special operational mode of the DDR SDRAM Interface. The
special modes are intended for initialization at power up.
000: Post Reset State – When the GMCH exits Reset (power-up or otherwise), the mode select field is
cleared to 000. Software is not expected to Write this value, however if this value is Written, there are no
side effects (no Self Refresh or any other special DDR SDRAM cycle).
During any Reset sequence, while power is applied and Reset is active, the GMCH deasserts all CKE
signals. After internal Reset is deasserted, CKE signals remain deasserted until this field is written to a
value different than 000. On this event, all CKE signals are asserted.
During Suspend (S3, S4), GMCH internal signal triggers DDR SDRAM Controller to flush pending
commands and enter all rows into Self-Refresh mode. As part of Resume sequence, GMCH will be
Reset , which will clear this bit field to 000 and maintain CKE signals deasserted. After internal Reset is
deasserted, CKE signals remain deasserted until this field is Written to a value different than 000. On this
event, all CKE signals are asserted.
During Entry to other low power states (C3, S1-M), GMCH internal signal triggers DDR SDRAM
Controller to flush pending commands and enter all rows in S1 and relevant rows in C3 (Based on
RPDNC3) into Self-Refresh mode. During exit to Normal mode, the GMCH signal triggers DDR SDRAM
Controller to Exit Self-Refresh and Resume Normal operation without S/W involvement.
001: NOP Command Enable – All CPU cycles to DDR SDRAM result in a NOP command on the DDR
SDRAM interface.
010: All Banks Pre-charge Enable – All CPU cycles to DDR SDRAM result in an All Banks Precharge
command on the DDR SDRAM interface.
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Datasheet