JG82855GMESL7VN Datasheet, PDF (156/213 Pages) Intel Corporation – Intel® 855GM/855GME Chipset Graphics and Memory Controller Hub (GMCH)

Functional Description
R
6.5.2.7
Panel Power Sequencing
This section provides details for the power sequence timing relationship of the panel power, the
backlight enable and the LVDS data timing delivery. In order to meet the panel power timing
specification requirements, two signals, PANELVDDEN and PANELBKLTEN are provided to
control the timing sequencing function of the panel and the backlight power supplies.
6.5.2.7.1 Panel Power Sequence States
A defined power sequence is recommended when enabling the panel or disabling the panel. The
set of timing parameters can vary from panel to panel vendor, provided that they stay within a
predefined range of values. The panel VDD power, the backlight on/off state and the LVDS clock
and data lines are all managed by an internal power sequencer.
A requested power-up sequence is only allowed to begin after the power cycle delay time
requirement T4 is met.
Figure 9. Panel Power Sequencing
T4 T1+T2 T5
Panel
On
TX T3
T4
Panel VDD
Enable
Panel
BackLight
Enable
Clock/Data Lines
Off
Off
Valid
Power On Sequence from off state and
Power Off Sequence after full On
156
Datasheet