JG82855GMESL7VN Datasheet, PDF (113/213 Pages) Intel Corporation – Intel® 855GM/855GME Chipset Graphics and Memory Controller Hub (GMCH)

Register Description
R
4.11 Intel^® 852GM GMCH Integrated Graphics Device
Registers (Device #2, Function #0)
This section contains the PCI configuration registers listed in order of ascending offset address.
Device #2 incorporates Function #0. See Section 4.2 for access nomenclature.
Note: C0F0 = Copy of Function #0 and U1F1 = Unique in Function #1.
Table 31. Integrated Graphics Device Configuration Space (Device #2, Function#0)
Register Name
Vendor Identification
Device Identification
PCI Command
PCI Status
Revision Identification
Class Code
Cache Line Size
Master Latency Timer
Header Type
Graphics Memory Range
Address
Memory Mapped Range
Address
IO Range
Subsystem Vendor ID
Subsystem ID
Video Bios ROM Base
Address
Interrupt Line
Interrupt Pin
Minimum Grant
Maximum Latency
Power Management
Capabilities
Power Management
Control
Register
Symbol
VID
DID
PCICMD
PCISTS
RID
CC
CLS
MLT
HDR
GMADR
MMADR
IOBAR
SVID
SID
ROMADR
INTRLINE
INTRPIN
MINGNT
MAXLAT
PMCAP
PMCS
Address
Offset
00h
02h
04h
06h
08h
09h
0Ch
0Dh
0Eh
10h
14h
18h
2Ch
2Eh
30h
3Ch
3Dh
3Eh
3Fh
D2h
D4h
Register
End
01h
03h
05h
07h
08h
0Bh
0Ch
0Dh
0Eh
13h
Default
Value
8086h
3582h
0000h
0090h
02h
030000h
00h
00h
00h
00000008h
Access
RO
RO
RO,R/W
RO
RO
RO
RO
RO
RO
RO,R/W
Regs in
Function#1
C0F0
C0F0
U1F1
U1F1
C0F0
U1F1
C0F0
C0F0
C0F0
U1F1
17h
00000000h
RO,R/W
U1F1
1Bh
00000001h
RO,R/W ⎯
2Dh
0000h
R/WO
C0F0
2Fh
0000h
R/ WO
C0F0
33h
00000000h
RO
C0F0
3Ch
00h
RO in F ⎯
#1,R/W
3Dh
01h
RO,
⎯
Reserved In
F#1
3Eh
00h
RO
C0F0
3Fh
00h
RO
C0F0
D3h
0221h
RO
C0F0
D5h
0000h
RO,R/W
U1F1
Datasheet
113