JG82855GMESL7VN Datasheet, PDF (88/213 Pages) Intel Corporation – Intel® 855GM/855GME Chipset Graphics and Memory Controller Hub (GMCH)

Register Description
R
4.9.3
PCICMD – PCI Command Register
Address Offset:
Default Value:
Access:
Size:
04-05h
0006h
Read Only, Read/Write
16 bits
Since Intel chipset Device #0 does not physically reside on PCI_A, many of the bits are not
implemented.
Bit
15:10
9
8
7
6
5
4
3
2
1
0
Description
Reserved
Fast Back-to-Back Enable (FB2B): This bit controls whether or not the master can do fast back-to-
back Write. Since Device #0 is strictly a target, this bit is not implemented and is hardwired to 0. Writes
to this bit position have no affect.
SERR Enable (SERRE): SERR# is not implemented by Function #1 of Device #0 of the GMCH and this
bit is hardwired to 0. Writes to this bit position have no effect.
Address/Data Stepping Enable (ADSTEP): Address/data stepping is not implemented in the GMCH,
and this bit is hardwired to 0. Writes to this bit position have no effect.
Parity Error Enable (PERRE): PERR# is not implemented by GMCH and this bit is hardwired to 0.
Writes to this bit position have no effect.
VGA Palette Snoop Enable (VGASNOOP): The GMCH does not implement this bit and it is hardwired
to a 0. Writes to this bit position have no effect.
Memory Write and Invalidate Enable (MWIE): The GMCH will never issue Memory Write and
Invalidate commands. This bit is therefore hardwired to 0. Writes to this bit position will have no effect.
Special Cycle Enable (SCE): The GMCH does not implement this bit and it is hardwired to a 0. Writes
to this bit position have no effect.
Bus Master Enable (BME): The GMCH is always enabled as a master on HI. This bit is hardwired to a
1. Writes to this bit position have no effect.
Memory Access Enable (MAE): The GMCH always allows access to main system memory. This bit is
not implemented and is hardwired to 1. Writes to this bit position have no effect.
I/O Access Enable (IOAE): This bit is not implemented in the GMCH and is hardwired to a 0. Writes to
this bit position have no effect.
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Datasheet