JG82855GMESL7VN Datasheet, PDF (185/213 Pages) Intel Corporation – Intel® 855GM/855GME Chipset Graphics and Memory Controller Hub (GMCH)

Video Filter Capacitors and Ferrite Bead Arranged in a
PI Configuration (One PI Filter Testability)
R
9 Video Filter Capacitors and Ferrite
Bead Arranged in a
PI Configuration (One PI Filter
Testability)
In the Intel 855GM/GME GMCH, testability for automated test equipment (ATE) board level
testing has been implemented as an XOR chain. An XOR-tree is a chain of XOR gates, each with
one input pin connected to it. The XOR Chain test mode is used by product engineers during
manufacturing and OEMs during board level connectivity tests. The main purpose of this test
mode is to detect connectivity shorts between adjacent pins and to check proper bonding between
I/O pads and I/O pins.
Figure 10. XOR–Tree Chain
VCC1_2
XOR
Out
Input
Input
Input
Input
Input
xor.vsd
The algorithm used for in–circuit test is as follows:
1. Drive all input pins to an initial logic level 1. Observe the output corresponding to scan chain
being tested.
2. Toggle pins one at a time starting from the first pin in the chain, continuing to the last pin,
from its initial logic level to the opposite logic level. Observe the output changes with each
pin toggle
Datasheet
185