JG82855GMESL7VN Datasheet, PDF (82/213 Pages) Intel Corporation – Intel® 855GM/855GME Chipset Graphics and Memory Controller Hub (GMCH)

Register Description
R
4.8.28
AGPCTRL – AGP Control Register (Device #0)
Address Offset:
Default Value:
Access:
Size:
B0–B1h
0000h
Read/Write
16 bits
This register provides for additional control of the AGP interface.
Bit 7 is visible to the operating system and must be retained in this position.
Bit
15:8
7
6:0
Description
Reserved
GTLB Enable (and GTLB Flush Control).
NOTE: This bit can be changed dynamically (i.e., while an access to GTLB occurs).
This bit must not be changed through memory mapped configuration register access space.
Reserved
4.8.29
AFT – AGP Functional Test Register (Device #0)
Address Offset:
Default Value:
Access:
Size:
B2–B3h
E9F0h
Read/Write, Read/WriteClear
16 bits
This register provides for additional control of the AGP interface.
Bit
15:11
10
9
8:4
3
Description
Retry Timer Time-Out Count (RTTOC): These bits control the retry time-out period (for initial data
phase) for the purpose of enhancing the system testability. These bits correspond to value loaded into
retry timer. Default value is 11101b (29d) for retry clock count of 32d (value +3).
PCI Write Streaming Disable (PCIBWSD): When this bit is set to ‘1’, PCI_B writes to DDR SDRAM
are disconnected at a 32 byte cache line boundary (write streaming is disabled). When this bit is set to
‘0’ (default), write streaming is enabled.
PCI Read Buffer Disable.
1 = When set to “1” the PCI Read Buffering mechanism is disabled. In this mode all data prefetched
and buffered for a PCI to DDR SDRAM read will be discarded when that read transaction terminates.
This bit defaults to “0”.
AGP/PCI1 Discard Timer Time-out Count. These bits control the length of AGP/PCI1 Delayed
Transaction discard time-out for the purpose of enhancing the system testability. Default value is
11111b (31d) for a discard count of 1024d ((value+1)*32).
PCI_B Write Combining Disable (PCIBWCD): When this bit is set to ‘1’, write combining is disabled
for host bus writes targeting the PCI_B bus (depends on configuration). When this bit is ‘0’ (default),
write combining is enabled.
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