JG82855GMESL7VN Datasheet, PDF (133/213 Pages) Intel Corporation – Intel® 855GM/855GME Chipset Graphics and Memory Controller Hub (GMCH)

Intel® 855GM/GME GMCH System Address Map
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The GMCH also forwards accesses to the Legacy VGA I/O ranges according to the settings in the
Device #1 configuration registers BCTRL (VGA Enable) and PCICMD1 (IOAE1), unless a
second adapter (monochrome) is present on the Hub interface/PCI (or ISA). The presence of a
second graphics adapter is determined by the MDAP configuration bit. When MDAP is set, the
GMCH will decode legacy monochrome IO ranges and forward them to the Hub interface. The
IO ranges decoded for the monochrome adapter are 3B4h, 3B5h, 3B8h, 3B9h, 3Bah and 3BFh.
Note: The GMCH Device #1 I/O address range registers defined above are used for all I/O space
allocation for any devices requiring such a window on AGP. These devices would include the
AGP device, PCI-66MHz/3.3V agents, and multifunctional AGP devices where one or more
functions are implemented as PCI devices.
The PCICMD1 register can disable the routing of I/O cycles to the AGP.
5.4.6
GMCH Decode Rules and Cross-Bridge Address Mapping
The address map described above applies globally to accesses arriving on any of the three
interfaces i.e. Host bus, IGD, and Hub interface.
5.4.7
5.4.7.1
Hub Interface Decode Rules
The GMCH accepts accesses from Hub interface to the following address ranges:
• All Memory Read and Write accesses to Main DDR SDRAM including PAM region (except
SMM space)
• All Memory Read/Write accesses to the Graphics Aperture (DRAM) defined by APBASE
and APSIZE.
• All Hub interface memory write accesses to AGP memory range defined by MBASE,
MLIMIT, PMBASE, and PMLIMIT.
• Memory writes to VGA range.
All Memory Reads from the Hub interface A that are targeted > 4-GB system memory range will
be terminated with Master Abort completion, and all Memory Writes (>4-GB) from the Hub
interface will be ignored.
Hub interface system memory accesses that fall elsewhere within the system memory range are
considered invalid and will be remapped to system memory address 0h, snooped on the Host Bus,
and dispatched to DDR SDRAM. Reads will return all 1’s with Master Abort completion. Writes
will have BE’s deasserted and will terminate with Master Abort if completion is required. I/O
cycles will not be accepted. They are terminated with Master Abort completion packets.
Hub Interface Accesses to GMCH that Cross Device Boundaries
Hub interface accesses are limited to 256 B (Bytes) but have no restrictions on crossing address
boundaries. A single Hub interface request may therefore span device boundaries (DDR SDRAM)
or cross from valid addresses to invalid addresses (or visa versa). The GMCH does not support
transactions that cross device boundaries. For Reads and for Writes requiring completion, the
GMCH will provide separate completion status for each naturally aligned 32-B or 64-B block. If
the starting address of a transaction hits a valid address, the portion of a request that hits that
Datasheet
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