JG82855GMESL7VN Datasheet, PDF (139/213 Pages) Intel Corporation – Intel® 855GM/855GME Chipset Graphics and Memory Controller Hub (GMCH)

Functional Description
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6.3.2 System Memory Organization and Configuration
6.3.2.1
Configuration Mechanism for SO-DIMMs
Detection of the type of DDR SDRAM installed on the SO-DIMM is supported via Serial
Presence Detect mechanism as defined in the JEDEC 200-pin SO- DIMM specification.
Before any cycles to the system memory interface can be supported, the GMCH DDR SDRAM
registers must be initialized. The GMCH must be configured for operation with the installed
system memory types. Detection of system memory type and size is done via the System
Management Bus (SMB) interface on the ICH4-M. This two-wire bus is used to extract the DDR
SDRAM type and size information from the Serial Presence Detect port on the DDR SDRAM
SO-DIMMs. DDR SDRAM SO-DIMMs contain a 5-pin Serial Presence Detect interface,
including SCL (serial clock), SDA (serial data) and SA[2:0]. Devices on the SMBus have a 7-bit
address. For the DDR SDRAM SO-DIMMs, the upper four bits are fixed at 1010b. The lower
three bits are strapped on the SA[2:0] pins. SCL and SDA are connected directly to the System
Management bus on the ICH4-M. Thus data is read from the Serial Presence Detect port on the
SO-DIMMs via a series of I/O cycles to the south bridge. The BIOS needs to determine the size
and type of system memory used for each of the rows of system memory in order to properly
configure the GMCH system memory interface.
For SMBus Configuration and Access of the Serial Presence Detect Ports, refer to the Intel®
82801DBM I/O Controller Hub 4 Mobile (ICH4-M) Datasheet (252337) for more details.
6.3.2.2 System Memory Register Programming
This section provides an overview of how the required information for programming the DDR
SDRAM registers is obtained from the Serial Presence Detect ports on the SO-DIMMs. The
Serial Presence Detect ports are used to determine Refresh Rate, MA and MD Buffer Strength,
row Type (on a row by row basis), DDR SDRAM Timings, row sizes and row page sizes. Table
36 lists a subset of the data available through the on board Serial Presence Detect ROM on each
SO-DIMM.
Table 36. Data Bytes on SO-DIMM Used for Programming DRAM Registers
Byte
2
3
4
5
11
12
17
Function
System Memory Type (DDR SDRAM)
Number of row addresses, not counting Bank Addresses
Number of Column Addresses
Number of SO-DIMM banks
ECC, No ECC
Refresh Rate/Type
Number Banks on each Device
Table 36 is only a subset of the defined SPD bytes on the SO-DIMMs. These bytes collectively
provide enough data for programming the GMCH DDR SDRAM registers.
Datasheet
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