JG82855GMESL7VN Datasheet, PDF (117/213 Pages) Intel Corporation – Intel® 855GM/855GME Chipset Graphics and Memory Controller Hub (GMCH)

Register Description
R
4.11.8
MLT – Master Latency Timer Register (Device #2)
Address Offset:
Default Value:
Access:
Size:
0Dh
00h
Read Only
8 bits
The IGD does not support the programmability of the master latency timer because it does not
perform bursts.
Bit
Description
7:0 Master Latency Timer Count Value – RO
4.11.9
HDR – Header Type Register (Device #2)
Address Offset:
Default Value:
Access:
Size:
0Eh
00h
Read Only
8 bits
This register contains the Header Type of the IGD.
Bit
Description
7
Multi Function Status (MFunc): Indicates if the device is a multi-function device.
6:0 Header Code (H): This is a 7-bit value that indicates the Header code for the IGD. This code has the
value 00h, indicating a type 0 configuration space format.
4.11.10
GMADR – Graphics Memory Range Address Register
(Device #2)
Address Offset:
Default Value:
Access:
Size:
10−13h
00000008h
Read/Write, Read Only
32 bits
IGD graphics system memory base address is specified in this register.
Bit
31:27
26
25:4
3
2:1
0
Description
Memory Base Address⎯R/W: Set by the OS, these bits correspond to address signals [31:26].
128-MB Address Mask – RO: 0 indicates 128-MB address
Address Mask⎯RO: Indicates (at least) a 32-MB address range.
Prefetchable Memory⎯RO: Enable prefetching.
Memory Type⎯RO: Indicate 32-bit address.
Memory/IO Space⎯RO: Indicate System Memory Space.
Datasheet
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