JG82855GMESL7VN Datasheet, PDF (137/213 Pages) Intel Corporation – Intel® 855GM/855GME Chipset Graphics and Memory Controller Hub (GMCH)

Functional Description
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6 Functional Description
6.1
Host Interface Overview
The GMCH front side bus uses source synchronous transfer for the address and data signals. The
address signals are double pumped and two addresses can be generated every bus clock. At
100 MHz bus frequency, the two address signals run at 200 MHz for a maximum address queue
rate of 50-M addresses/sec. The data is quad pumped and an entire 64-B cache line can be
transferred in two bus clocks. At 100 MHz bus frequency, the data signals run at 400 MHz for a
maximum bandwidth of 3.2- GB/s. The GMCH supports a 8-deep IOQ (In-Order-Queue) using
the Intel Pentium M processor or Intel Celeron M processor.
6.2
Dynamic Bus Inversion
The GMCH supports dynamic bus inversion (DBI) when driving and receiving data from the Host
Bus. DBI limits the number of data signals that are driven to a low voltage on each quad pumped
data phase. This decreases the power consumption of the GMCH. DINV[3:0]# indicates if the
corresponding 16 bits of data are inverted on the bus for each quad pumped data phase:
Table 35. Relation of DBI Bits to Data Bits
DINV[3:0]
DINV[0]#
DINV[1]#
DINV[2]#
DINV[3]#
Data Bits
HD[15:0]#
HD[31:16]#
HD[47:32]#
HD[63:48]#
6.2.1
Whenever the CPU or the GMCH drives data, each 16-bit segment is analyzed. If more than eight
of the 16 signals would normally be driven low on the bus the corresponding DINV# signal will
be asserted and the data will be inverted prior to being driven on the bus. Whenever the CPU or
the GMCH receives data it monitors DINV[3:0]# to determine if the corresponding data segment
should be inverted.
System Bus Interrupt Delivery
The Intel Pentium M processor and Intel Celeron M processor support system bus interrupt
delivery. It does not support the APIC serial bus interrupt delivery mechanism. Interrupt related
messages are encoded on the system bus as Interrupt Message transactions. System bus interrupts
may originate from the processor on the system bus, or from a downstream device on the Hub
interface.
Datasheet
137