JG82855GMESL7VN Datasheet, PDF (101/213 Pages) Intel Corporation – Intel® 855GM/855GME Chipset Graphics and Memory Controller Hub (GMCH)

Register Description
R
4.9.17
Bit
Description
011: Mode Register Set Enable – All CPU cycles to DDR SDRAM result in a Mode Register set
command on the DDR SDRAM Interface. Host address lines are mapped to DDR SDRAM address lines
in order to specify the command sent. Host address HA[13:3] are mapped to Memory address
SMA[11,9:0]. SMA3 must be driven to 1 for interleave wrap type.
For Double Data Rate
MA[6:4] needs to be driven based on the value programmed in the CAS# Latency field.
CAS Latency MA[6:4]
1.5 Clocks
001
2.0 Clocks
010
2.5 Clocks
110
SMA[7] should always be driven to a 0.
SMA[8] Should be driven to a 1 for DLL Reset and 1 for Normal Operation.
SMA[12:9] must be driven to 00000.
BIOS must calculate and drive the correct host address for each row of Memory such that the correct
command is driven on the SMA[12:0] lines. Note that SMAB[5,4,2,1]# are inverted from SMA[5,4,2,1];
BIOS must account for this.
100: Extended Mode Register Set Enable – All CPU cycles to DDR SDRAM result in an “Extended
Mode register set” command on the DDR SDRAM Interface. Host address lines are mapped to DDR
SDRAM address lines in order to specify the command sent. Host address lines are mapped to DDR
SDRAM address lines in order to specify the command sent. Host address HA[13:3] are mapped to
Memory address SMA[11,9:0]. SMA[0] = 0 for DLL enable and 1 for DLL disable. All the other SMA lines
are driven to 0’s. Note that SMAB[5,4,2,1]# are inverted from SMA[5,4,2,1]; BIOS must account for this.
101: Reserved
110: CBR Refresh Enable – In this mode all CPU cycles to DDR SDRAM result in a CBR cycle on the
DDR SDRAM interface
111: Normal operation
3:0
Reserved
DTC – DRAM Throttling Control Register (Device #0)
Offset Address:
Default Value:
Access:
Size:
A0–A3h
00000000h
Read/Write/Lock
32 bits
Throttling is independent for system memory banks, GMCH Writes, and Thermal Sensor Trips.
Read and Write Bandwidth is measured independently for each bank. If the number of Octal -
Words (16 bytes) Read/Written during the window defined below (Global DDR SDRAM
Sampling Window: GDSW) exceeds the DDR SDRAM Bandwidth Threshold, then the DDR
SDRAM Throttling mechanism will be invoked to limit DDR SDRAM Reads/Writes to a lower
bandwidth checked over smaller time windows. The throttling will be active for the remainder of
the current GDSW and for the next GDSW after which it will return to Non-Throttling mode. The
throttling mechanism accounts for the actual bandwidth consumed during the sampling window,
by reducing the allowed bandwidth within the smaller throttling window based on the bandwidth
Datasheet
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