JG82855GMESL7VN Datasheet, PDF (159/213 Pages) Intel Corporation – Intel® 855GM/855GME Chipset Graphics and Memory Controller Hub (GMCH)

Functional Description
R
6.5.3
6.5.4
6.5.5
AGP Command
C/BE[3:0]#
Encoding
Cycle Destination
GMCH Host Bridge
Response as PCIx Target
Hi-Priority Long
Read
1001
Flush
Reserved
Fence
Reserved
Reserved
Reserved
1010
1011
1100
1101
1110
1111
Main Memory
The Hub interface
GMCH
N/A
GMCH
N/A
N/A
N/A
High Priority Read
Complete locally with random data; does not go
to the hub interface
Complete with QW of Random Data
No Response
No Response - Flag inserted in GMCH request
queue
No Response
No Response
No Response
NOTE: N/A refers to a function that is not applicable.
As a target of an AGP cycle, the GMCH supports all the transactions targeted at main memory
(summarized in the table above). The GMCH supports both normal and high-priority, read and
write requests. The GMCH does not support AGP cycles to the hub interface. PIPE# and SBA
cycles are assumed not to require coherency management and all AGP initiator accesses to main
memory using AGP PIPE# or SBA protocol are treated as non-snoopable cycles. These accesses
are directed to the AGP aperture in main memory that is programmed as either uncacheable (UC)
memory or write combining (WC) in the processor’s MTRRs.
AGP Transaction Ordering
The GMCH observes transaction ordering rules as defined by the AGP Interface Specification
Rev 2.0.
AGP Signal Levels
The 4X data transfers use 1.5 V signaling levels as described in the AGP Interface Specification
Rev 2.0. The GMCH supports 1X/2X data transfers using 1.5 V signaling levels.
4X AGP Protocol
In addition to the 1X and 2X AGP protocol, the GMCH supports 4X AGP read and write data
transfers and 4X sideband address generation. The 4X operation is compliant with AGP 2.0
specification.
The GMCH indicates that it supports 4X data transfers through RATE[2] (bit 2) of the AGP
Status Register. When DATA_RATE[2] of the AGP Command Register is set to 1 during system
initialization, the GMCH performs AGP read/write data transactions using 4X protocol. This bit is
not dynamic. Once this bit is set during initialization, the data transfer rate will not change.
Datasheet
159