JG82855GMESL7VN Datasheet, PDF (162/213 Pages) Intel Corporation – Intel® 855GM/855GME Chipset Graphics and Memory Controller Hub (GMCH)

Functional Description
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• Fast Back-to-Back Transactions. GMCH as a target supports fast back-to-back cycles from an
AGP FRAME# initiator.
As an initiator of AGP FRAME# cycle, the GMCH only supports the following transactions:
• Memory Read and Memory Read Line. GMCH supports reads from host to AGP. GMCH
does not support reads from the hub interface to AGP.
• Memory Read Multiple. This command is not supported by the GMCH as an AGP FRAME#
initiator.
• Memory Write. GMCH initiates AGP FRAME# cycles on behalf of the host or the hub
interface. GMCH does not issue Memory Write and Invalidate as an initiator. GMCH does
not support write merging or write collapsing. GMCH allows non-snoopable write
transactions from the hub interface to the AGP bus.
• I/O Read and Write. I/O read and write from the host are sent to the AGP bus. I/O base and
limit address range for AGP bus are programmed in AGP FRAME# configuration registers.
All other accesses that do not correspond to this programmed address range are forwarded to
the hub interface.
• Exclusive Access. GMCH does not issue a locked cycle on the AGP bus on behalf of either
the host or the hub interface. The hub interface and host locked transactions to AGP are
initiated as unlocked transactions by the GMCH on the AGP bus.
• Configuration Read and Write. Host Configuration cycles to AGP are forwarded as Type 1
Configuration Cycles.
• Fast Back-to-Back Transactions. GMCH as an initiator does not perform fast back-to-back
cycles.
GMCH Retry/Disconnect Conditions
The GMCH generates retry/disconnect according to the AGP Specification rules when being
accessed as a target from the AGP FRAME# device.
Delayed Transaction
When an AGP FRAME#-to-DRAM read cycle is retried by the GMCH, it is processed internally
as a Delayed Transaction.
The GMCH supports the delayed transaction mechanism on the AGP target interface for the
transactions issued using AGP FRAME# protocol. This mechanism is compatible with the PCI
2.1 Specification. The process of latching all information required to complete the transaction,
terminating with retry, and completing the request without holding the master in wait-states is
called a delayed transaction. The GMCH latches the address and command when establishing a
Delayed Transaction. The GMCH generates a Delayed transaction on the AGP only for AGP
FRAME# to DRAM read accesses. The GMCH does not allow more than one Delayed
transaction access from AGP at any time.
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Datasheet