JG82855GMESL7VN Datasheet, PDF (120/213 Pages) Intel Corporation – Intel® 855GM/855GME Chipset Graphics and Memory Controller Hub (GMCH)

Register Description
R
4.11.16
INTRLINE – Interrupt Line Register (Device #2)
Address Offset:
Default Value:
Access:
Size:
3Ch
00h
Read/Write
8 bits
Bit
Description
7:0
Interrupt Connection: Used to communicate interrupt line routing information. POST software Writes
the routing information into this register as it initializes and configures the system. The value in this
register indicates which input of the System Interrupt controller that the device’s interrupt pin is connected
to.
4.11.17
INTRPIN – Interrupt Pin Register (Device #2)
Address Offset:
Default Value:
Access:
Size:
3Dh
01h
Read Only
8 bits
Bit
Description
7:0
Interrupt Pin: As a single function device, the IGD specifies INTA# as its interrupt pin. 01h=INTA#. For
Function #1, this register is set to 00h.
4.11.18
MINGNT – Minimum Grant Register (Device #2)
Address Offset:
Default Value:
Access:
Size:
3Eh
00h
Read Only
8 bits
Bit
Description
7:0 Minimum Grant Value: The IGD does not burst as a PCI compliant master.
4.11.19
MAXLAT – Maximum Latency Register (Device #2)
Address Offset:
Default Value:
Access:
Size:
3Fh
00h
Read Only
8 bits
Bit
Description
7:0 Maximum Latency Value: Bits[7:0]=00h. The IGD has no specific requirements for how often it needs to
access the PCI bus.
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Datasheet