JG82855GMESL7VN Datasheet, PDF (201/213 Pages) Intel Corporation – Intel® 855GM/855GME Chipset Graphics and Memory Controller Hub (GMCH)

Intel® 855GM/GME GMCH Strap Pins
R
10 Intel^® 855GM/GME GMCH Strap
Pins
10.1 Strapping Configuration
Table 54. Strapping Signals and Configuration
Pin Name
HSYNC
Strap Description
XOR Chain Test
VSYNC
ALL Z Test
LCLKCTLB
VTT Voltage Select
DVODETECT
GST[2]
DVO Select (If
DVODETECT=0 during
Reset, ADDID[7:0] is
latched to the ADDID
Register) ⁽¹⁾
Clock Config: Bit_2 ⁽¹⁾
GST[1]
Clock Config: Bit_1⁽¹⁾
Configuration
Low = Normal Ops (Default)
High = XOR Test On
Low = Normal Ops (Default)
High = AllZ Test On
High = 1.05 V – Intel Pentium
M Processor / Intel Celeron M
Processor
Low = DVO (Default)
High = Reserved
I/F Type
GPIO
GPIO
GPIO
DVO
Please refer to Device #0
Function #3 (HPLLCC
Register) for proper GST[2:0]
settings
DVO
GST[0]
Clock Config: Bit_0⁽¹⁾
OUT
Buffer Type
OUT
OUT
BI
Out:
0) Before CPURST#, there is
internal pull-down
1) Just out of CPURST#:
These pins are Hi-Z
2) C3: these pins are Hi-Z
3) S1-M: these pins are Hi-Z
4) Internal GFX D1/D3: these
pins are Hi-Z
5) S3: these pins are Power
down
6) S4/S5: these pins are
Power down
NOTES:
1.External pull-ups/downs will be required on the board to enable the non-default state of the straps.
Note: All strap signals are sampled with respect to the leading edge of the Intel 855GM/GME GMCH
PWROK In signal.
§
Datasheet
201