JG82855GMESL7VN Datasheet, PDF (6/213 Pages) Intel Corporation – Intel® 855GM/855GME Chipset Graphics and Memory Controller Hub (GMCH)

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4.11.21 PMCS – Power Management Control/Status Register (Device #2) ... 121
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Intel^® 855GM/GME GMCH System Address Map .......................................................... 123
5.1 System Memory Address Ranges...................................................................... 123
5.2 DOS Compatibility Area ..................................................................................... 125
5.3 Extended System Memory Area......................................................................... 127
5.4 Main System Memory Address Range (0010_0000h to Top of Main Memory). 128
5.4.1 15-MB – 16-MB Window..................................................................... 128
5.4.2 Pre-allocated System Memory............................................................ 128
5.4.2.1 Extended SMRAM Address Range (HSEG and TSEG) ... 129
5.4.2.2 HSEG ................................................................................ 129
5.4.2.3 TSEG ................................................................................. 129
5.4.2.4 Dynamic Video Memory Technology (DVMT)................... 129
5.4.2.5 PCI Memory Address Range (Top of Main System Memory
to 4 GB) ............................................................................. 129
5.4.2.6 APIC Configuration Space (FEC0_0000h -FECF_FFFFh,
FEE0_0000h- FEEF_FFFFh) ............................................ 130
5.4.2.7 High BIOS Area (FFE0_0000h -FFFF_FFFFh)................. 130
5.4.3
5.4.4
5.4.5
5.4.6
System Management Mode (SMM) Memory Range .......................... 130
5.4.3.1 SMM Space Restrictions ................................................... 131
5.4.3.2 SMM Space Definition ....................................................... 131
System Memory Shadowing ............................................................... 132
I/O Address Space.............................................................................. 132
5.4.5.1 AGP/PCI I/O Address Mapping ......................................... 132
GMCH Decode Rules and Cross-Bridge Address Mapping............... 133
5.4.7 Hub Interface Decode Rules............................................................... 133
5.4.7.1 Hub Interface Accesses to GMCH that Cross Device
Boundaries ........................................................................ 133
5.4.7.2 AGP Interface Decode Rules ............................................ 134
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Functional Description .................................................................................................... 137
6.1 Host Interface Overview ..................................................................................... 137
6.2 Dynamic Bus Inversion....................................................................................... 137
6.2.1 System Bus Interrupt Delivery ............................................................ 137
6.2.2 Upstream Interrupt Messages ............................................................ 138
6.3 System Memory Interface .................................................................................. 138
6.3.1 DDR SDRAM Interface Overview ....................................................... 138
6.3.2 System Memory Organization and Configuration............................... 139
6.3.2.1 Configuration Mechanism for SO-DIMMs ......................... 139
6.3.2.2 System Memory Register Programming ........................... 139
6.3.3 DDR SDRAM Performance Description ............................................. 140
6.3.3.1 Data Integrity (ECC) .......................................................... 140
6.4 Integrated Graphics Overview............................................................................ 140
6.4.1 3D/2D Instruction Processing ............................................................. 141
6.4.2
3D Engine ........................................................................................... 141
6.4.2.1 Bi-Cubic Filtering (Intel^® 855GME GMCH)........................ 142
6.4.2.2 Video Mixer Rendering (Intel^® 855GME GMCH) .............. 142
6.4.2.3 Setup Engine ..................................................................... 142
6.4.2.4 Viewport Transform and Perspective Divide ..................... 142
6.4.2.5 3D Primitives and Data Formats Support.......................... 143
6.4.2.6 Pixel Accurate Fast Scissoring and Clipping Operation.... 143
6.4.2.7 Backface Culling................................................................ 143
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Datasheet