JG82855GMESL7VN Datasheet, PDF (97/213 Pages) Intel Corporation – Intel® 855GM/855GME Chipset Graphics and Memory Controller Hub (GMCH)

Register Description
R
Bit
3:2
1:0
Description
DDR SDRAM RAS# to CAS# Delay (tRCD): This bit controls the number of clocks inserted between a
Row Activate command and a Read or Write command to that row.
Encoding tRCD
00:
4 DDR SDRAM Clocks (DDR 333 SDRAM)
01:
3 DDR SDRAM Clocks
10:
2 DDR SDRAM Clocks
11:
Reserved
DDR SDRAM RAS# Precharge (tRP): This bit controls the number of clocks that are inserted between
a row precharge command and an activate command to the same row.
Encoding
tRP
00:
4 DDR SDRAM Clocks (DDR 333 SDRAM)
01:
3 DDR SDRAM Clocks
10:
2 DDR SDRAM Clocks
11:
Reserved
Datasheet
97