JG82855GMESL7VN Datasheet, PDF (55/213 Pages) Intel Corporation – Intel® 855GM/855GME Chipset Graphics and Memory Controller Hub (GMCH)

Register Description
R
4.5
Register Definitions
The GMCH contains four sets of software accessible registers accessed via the Host CPU I/O
Address Space, and they are as follows:
• Control registers: I/O Mapped into the CPU I/O Space, which control access to PCI
Configuration Space via Configuration Mechanism #1 in the PCI 2.2 specification.
• Internal Configuration registers: residing within the GMCH, they are partitioned into two
logical device register sets (“logical” since they reside within the single physical device). The
first register set is dedicated to Host-HI Bridge functionality (i.e. DDR SDRAM
configuration, other chip-set operating parameters and optional features). The second register
block is for the integrated graphics functions.
• Internal Memory Mapped Configuration registers: reside in the GMCH Device #0.
• Internal Memory Mapped Configuration registers and Legacy VGA registers: reside in
the GMCH Device #2 that controls the Integrated Graphics Controller.
The GMCH internal registers (I/O Mapped and Configuration registers) are accessible by the Host
CPU. The registers can be accessed as Byte, Word (16-bit), or Dword (32-bit) quantities, with the
exception of CONFIG_ADDRESS, which can only be accessed as a Dword. All multi-byte
numeric fields use “Little Endian Byte Ordering” (i.e., lower addresses contain the least
significant parts of the field).
Reserved Bits
Some of the GMCH registers described in this section contain Reserved bits. These bits are
labeled “Reserved”. Software must deal correctly with fields that are Reserved. On Reads,
software must use appropriate Masks to extract the defined bits and not rely on Reserved bits
being any particular value. On Writes, software must ensure that the values of Reserved bit
positions are preserved. That is, the values of Reserved bit positions must first be Read, Merged
with the new values for other bit positions and then Written back.
Note: The software does not need to perform Read, Merge, and Write operations for the Configuration
Address register.
Default Value upon Reset
Upon a Full Reset, the GMCH sets all of its Internal Configuration registers to a predetermined
default state. Some register values at Reset are determined by external strapping options. The
default state represents the minimum functionality feature set required to successfully bring up the
system. Hence, it does not represent the optimal system configuration. It is the responsibility of
the system initialization software (usually BIOS) to properly determine the DDR SDRAM
configurations, operating parameters, and optional system features that are applicable and to
program the GMCH registers accordingly.
Datasheet
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