JG82855GMESL7VN Datasheet, PDF (115/213 Pages) Intel Corporation – Intel® 855GM/855GME Chipset Graphics and Memory Controller Hub (GMCH)

Register Description
R
Bit
2
1
0
Description
Bus Master Enable (BME) ⎯R/W: This bit determines if the IGD is to function as a PCI compliant
master.
0= Disable IGD bus mastering (default).
1 = Enable IGD bus mastering.
Memory Access Enable (MAE) ⎯R/W: This bit controls the IGD’s response to System Memory Space
accesses.
0= Disable (default).
1 = Enable.
I/O Access Enable (IOAE) ⎯R/W: This bit controls the IGD’s response to I/O Space accesses.
0 = Disable (default).
1 = Enable.
4.11.4
PCISTS – PCI Status Register (Device #2)
Address Offset:
Default Value:
Access:
Size:
06−07h
0090h
Read Only
16 bits
PCISTS is a 16-bit status register that reports the occurrence of a PCI compliant master abort and
PCI compliant target abort. PCISTS also indicates the DEVSEL# timing that has been set by the
IGD.
Bit
Description
15
Detected Parity Error (DPE): Since the IGD does not detect parity, this bit is always set to 0.
14
Signaled System Error (SSE) – RO
13
Received Master Abort Status (RMAS) – RO
12
Received Target Abort Status (RTAS) – RO
11
Signaled Target Abort Status (STAS) – RO
10:9 DEVSEL# Timing (DEVT) – RO
8
Data Parity Detected (DPD) – RO
7
Fast Back-to-Back (FB2B) – RO
6
User Defined Format (UDF) – RO
5
66 MHz PCI Capable (66C) – RO
4
CAP LIST: This bit is set to 1 to indicate that the register at 34h provides an offset into the Function’s PCI
Configuration Space containing a pointer to the location of the first item in the list.
3:0
Reserved
Datasheet
115