JG82855GMESL7VN Datasheet, PDF (31/213 Pages) Intel Corporation – Intel® 855GM/855GME Chipset Graphics and Memory Controller Hub (GMCH)

Signal Descriptions
R
Signal Name
DRDY#
HA[31:3]#
HADSTB[1:0]#
HD[63:0]#
HDSTBP[3:0]#
HDSTBN[3:0]#
HIT#
HITM#
HLOCK#
HREQ[4:0]#
HTRDY#
Type
I/O
AGTL+
I/O
AGTL+
I/O
AGTL+
I/O
AGTL+
I/O
AGTL+
I/O
AGTL+
I/O
AGTL+
I/O
AGTL+
I/O
AGTL+
O
AGTL+
Description
Data Ready: Asserted for each cycle that data is transferred.
Host Address Bus: HA[31:3]# connects to the CPU address bus. During processor
cycles the HA[31:3]# are inputs. The GMCH drives HA[31:3]# during snoop cycles on
behalf of Hub interface. HA[31:3]# are transferred at 2X rate. Note that the address is
inverted on the CPU bus.
Host Address Strobe: HA[31:3]# connects to the CPU address bus. During CPU
cycles, the source synchronous strobes are used to transfer HA[31:3]# and
HREQ[4:0]# at the 2X transfer rate.
Strobe
Address Bits
HADSTB[0]# HA[16:3]#, HREQ[4:0]#
HADSTB[1]# HA[31:17]#
Host Data: These signals are connected to the CPU data bus. HD[63:0]# are
transferred at 4X rate. Note that the data signals are inverted on the CPU bus.
Differential Host Data Strobes: The differential source synchronous strobes are
used to transfer HD[63:0]# and DINV[3:0]# at the 4X transfer rate.
Strobe
Data Bits
HDSTBP[3]#, HDSTBN[3]#
HD[63:48]#, DINV[3]#
HDSTBP[2]#, HDSTBN[2]#
HD[47:32]#, DINV[2]#
HDSTBP[1]#, HDSTBN[1]#
HD[31:16]#, DINV[1]#
HDSTBP[0]#, HDSTBN[0]#
HD[15:0]#, DINV[0]#
Hit: Indicates that a caching agent holds an unmodified version of the requested line.
Also, driven in conjunction with HITM# by the target to extend the snoop window.
Hit Modified: Indicates that a caching agent holds a modified version of the requested
line and that this agent assumes responsibility for providing the line. Also, driven in
conjunction with HIT# to extend the snoop window.
Host Lock: All CPU bus cycles sampled with the assertion of HLOCK# and ADS#,
until the negation of HLOCK# must be atomic, i.e. no Hub interface snoopable access
to system memory is allowed when HLOCK# is asserted by the CPU.
Host Request Command: Defines the attributes of the request. HREQ[4:0]# are
transferred at 2X rate. Asserted by the requesting agent during both halves of the
Request Phase. In the first half the signals define the transaction type to a level of
detail that is sufficient to begin a snoop request. In the second half the signals carry
additional information to define the complete transaction type.
The transactions supported by the GMCH Host Bridge are defined in the Host Interface
section of this document.
Host Target Ready: Indicates that the target of the processor transaction is able to
enter the data transfer phase.
Datasheet
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