JG82855GMESL7VN Datasheet, PDF (35/213 Pages) Intel Corporation – Intel® 855GM/855GME Chipset Graphics and Memory Controller Hub (GMCH)

Signal Descriptions
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3.3.2 AGP Flow Control Signals
Table 6. AGP Flow Control Signals
Signal Name
GRBF#
GWBF#
Type
I
AGP
I
AGP
Description
Read Buffer Full: Read buffer full indicates if the master is ready to accept previously
requested low priority read data. When RBF# is asserted the GMCH is not allowed to
initiate the return low priority read data. That is, the GMCH can finish returning the data
for the request currently being serviced. RBF# is only sampled at the beginning of a
cycle.
If the AGP master is always ready to accept return read data then it is not required to
implement this signal.
During FRAME# Operation: This signal is not used during AGP FRAME# operation.
Write-Buffer Full: indicates if the master is ready to accept Fast Write data from the
GMCH. When WBF# is asserted the GMCH is not allowed to drive Fast Write data to
the AGP master. WBF# is only sampled at the beginning of a cycle.
If the AGP master is always ready to accept fast write data then it is not required to
implement this signal.
During FRAME# Operation: This signal is not used during AGP FRAME# operation.
3.3.3 AGP Status Signals
Table 7. AGP Status Signal Descriptions
Signal Name
GST[2:0]
Type
O
AGP
Status: Provides
information from the
arbiter to an AGP
Master on what it may
do. ST[2:0] only have
meaning to the master
when its GNT# is
asserted. When GNT#
is deasserted these
signals have no
meaning and must be
ignored.
ST[2:0
000
001
010
011
100
101
110
110
Description
Meaning
Previously requested low priority read data is being
returned to the master
Previously requested high priority read data is being
returned to the master
The master is to provide low priority write data for a
previously queued write command
The master is to provide high priority write data for a
previously queued write command.
Reserved
Reserved
Reserved
The master has been given permission to start a bus
transaction. The master may queue AGP requests by
asserting PIPE# or start a PCI transaction by
asserting FRAME#.
Datasheet
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