JG82855GMESL7VN Datasheet, PDF (96/213 Pages) Intel Corporation – Intel® 855GM/855GME Chipset Graphics and Memory Controller Hub (GMCH)

Register Description
R
Bit
14:12
11
10:9
8:7
6:5
4
Description
Refresh Cycle Time (tRFC):
Refresh Cycle Time is measured for a given row from REF command (to perform a refresh) until
following ACT to same row (to perform a Read or Write). It is tracked separately from tRC for DDR
SDRAM.
Current DDR SDRAM spec requires tRFC of 75 ns (DDR266) and 80 ns (DDR200). Therefore, this field
will be set to 8 clocks for DDR200, 10 clocks for DDR266.
Encoding tRFC
000:
14 clocks
001:
13 clocks
010:
12 clocks
011:
11 clocks
100:
10 clocks
101:
9 clocks
110:
8 clocks
111:
7 clocks
Activate to Precharge delay (tRAS), MAX:
This bit controls the maximum number of clocks that a DDR SDRAM bank can remain open. After this
time period, the system memory Controller will guarantee to pre-charge the bank. Note that this time
period may or may not be set to overlap with time period that requires a refresh to happen.
The DDR SDRAM Controller includes a separate tRAS-MAX counter for every supported bank. With a
maximum of four rows and four banks per row, there are 16 counters.
0: 120 micro-seconds
1: Reserved.
Activate to Precharge delay (tRAS), MIN:
This bit controls the number of DDR SDRAM clocks for tRAS MIN
00: 8 Clocks
01: 7 Clocks
10: 6 Clocks
11: 5 Clocks
Reserved
CAS# Latency (tCL):
Encoding
DDR SDRAM CL
00:
2.5
01:
2
10:
Reserved
11:
Reserved
Reserved
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Datasheet