JG82855GMESL7VN Datasheet, PDF (154/213 Pages) Intel Corporation – Intel® 855GM/855GME Chipset Graphics and Memory Controller Hub (GMCH)

Functional Description
R
6.5.1.1
6.5.1.2
6.5.2
6.5.2.1
Integrated RAMDAC
The display function contains a 350 MHz, integrated, 24-bit, RAM-based Digital-to-Analog
Converter (RAMDAC) that transforms up to 2048X1536 digital pixels at a maximum refresh rate
of 75 Hz. Three, 8-bit DACs provide the R, G, and B signals to the monitor.
DDC (Display Data Channel)
DDC is defined by VESA. It allows communication between the host system and display. Both
configuration and control information can be exchanged allowing plug-and-play systems to be
realized. Support for DDC 1 and 2 is implemented.
Digital Display Interface
Dedicated LVDS Interface
The GMCH has a dedicated ANSI/TIA/EIA –644-1995 Specification compliant dual channel LFP
LVDS interface that can support TFT panel resolutions up to UXGA with a maximum pixel
format of 18 bpp (with SSC supported frequency range from 35 MHz to 112 MHz (single
channel/dual channel).
The display pipe selected by the LVDS display port is programmed with the panel timing
parameters that are determined by installed panel specifications or read from an onboard EDID
ROM. The programmed timing values are then “locked” into the registers to prevent unwanted
corruption of the values. From that point on, the display modes are changed by selecting a
different source size for that pipe, programming the VGA registers, or selecting a source size and
enabling the VGA. The timing signals will remain stable and active through mode changes. These
mode changes include VGA to VGA, VGA to HiRes, HiRes to VGA, and HiRes to HiRes.
The transmitter can operate in a variety of modes and supports several data formats. The serializer
supports 6-bit or 8-bit color and single or dual channel operating modes. The display stream from
the display pipe is sent to the LVDS transmitter port at the dot clock frequency, which is
determined by the panel timing requirements. The output of LVDS is running at a fixed multiple
of the dot clock frequency, which is determined by the mode of operation; single or dual channel.
Depending on configuration and mode, a single channel can take 18-bits of RGB pixel data plus 3
bits of timing control (HSYNC/VSYNC/DE) and output them on three differential data pair
outputs; or 24 bits of RGB plus 3 bits of timing control output on four differential data pair
outputs. A dual channel interface converts 36 bits or 48 bits of color information plus the 3 bits of
timing control and outputs it on six or eight sets of differential data outputs.
This display port is normally used in conjunction with the pipe functions of panel scaling and a 6-
bit to 8-bit dither. This display port is also used in conjunction with the panel power sequencing
and additional associated functions.
When enabled, the LVDS constant current drivers consume significant power. Individual pairs or
sets of pairs can be selected to be powered down when not used. When disabled, individual or
sets of pairs will enter a low power state. When the port is disabled all pairs enters a low power
mode. The panel power sequencing can be set to override the selected power state of the drivers
during power sequencing.
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Datasheet