JG82855GMESL7VN Datasheet, PDF (187/213 Pages) Intel Corporation – Intel® 855GM/855GME Chipset Graphics and Memory Controller Hub (GMCH)

Video Filter Capacitors and Ferrite Bead Arranged in a
PI Configuration (One PI Filter Testability)
R
9.2
XOR Chain Differential Pairs
Table 50 provides differential signals in the XOR chains that must be treated as pairs. Pin1 and
Pin2 as shown below need to drive to the opposite value always.
Table 50. Differential Signals in the XOR Chains
Pin1
DVOCCLK#
HLSTB#
Pin2
DVOCCLK
HLSTB
XOR Chain
DVO XOR 2
HUB XOR
9.3
XOR Chain Exclusion List
See Table 51 for a list of pins that are not included in the XOR chains (excluding all
VCC/VSS/VTT).
Note: Connectivity column is used to identify what need to be driven on that particular pin during XOR
chain test mode.
Table 51. XOR Chain Exclusion List of Pins
Item#
IN/OUT
Ball
1
IN
Y3
2
-
W1
3
-
T2
4
-
U2
5
-
F1
6
-
D1
7
IN
J11
8
IN
B7
9
-
E8
10
-
C9
11
-
D9
12
-
C8
13
-
D8
14
A7
15
-
A8
16
-
D12
17
-
A10
Pin/VHDL
GCLKIN
HLVREF
HLRCOMP
PSWING
GVREF
DVORCOMP
PWROK
DREFCLK
REFSET
BLUE
BLUE#
GREEN
GREEN#
RED
RED#
LVREFH
LIBG
I/O Type
PLL CLK
Analog
Analog
Analog
Analog
Analog
CMOS
PLL CLK
Analog
Analog
Analog
Analog
Analog
Analog
Analog
Analog
Analog
Voltage
3.3
1/3 VCCHL
N/A
N/A
1/2
VCCDVO
N/A
3.3
3.3
N/A
N/A
N/A
N/A
N/A
N/A
N/A
1.1
N/A
Connectivity
0
0.4
N/A
N/A
0.75
N/A
N/A
0
N/A
N/A
N/A
N/A
N/A
N/A
N/A
1.1
N/A
Datasheet
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