JG82855GMESL7VN Datasheet, PDF (54/213 Pages) Intel Corporation – Intel® 855GM/855GME Chipset Graphics and Memory Controller Hub (GMCH)

Register Description
R
4.4.2
Primary PCI and Downstream Configuration Mechanism
If the Bus Number in the CONFIG_ADDRESS is non-zero, and is less than the value in the Host-
AGP/PCI_B device’s Secondary bus number register or greater than the value in the Host-
AGP/PCI_B device’s Subordinate bus number register, the GMCH will generate a Type 1 Hub
interface Configuration Cycle. A[1:0] of the Hub interface request packet for the Type 1
configuration cycle will be “01”. This Hub interface configuration cycle will be sent over Hub
interface.
If the cycle is forwarded to the ICH4-M via Hub interface, the ICH4-M compares the non-zero
Bus Number with the Secondary bus number and Subordinate bus number registers of its PCI-to-
PCI bridges to determine if the configuration cycle is meant for Primary PCI, one of the ICH4-
M’s Hub interfaces, or a downstream PCI bus.
4.4.3 AGP/PCI_B Bus Configuration Mechanism
From the chip-set configuration perspective, AGP/PCI_B is seen as PCI bus interfaces residing on
a Secondary Bus side of the “virtual” PCI-to-PCI bridges referred to as the GMCH Host-
PCI_B/AGP bridge. On the Primary bus side, the “virtual” PCI-to-PCI bridge is attached to PCI
Bus #0. Therefore the Primary bus number register is hardwired to “0”. The “virtual” PCI-to-PCI
bridge entity converts Type #1 PCI Bus Configuration cycles on PCI Bus #0 into Type 0 or Type
1 configuration cycles on the AGP/PCI_B interface. Type 1 configuration cycles on PCI Bus #0
that have a Bus number that matches the Secondary bus number of the GMCH ’s “virtual” Host-
to-PCI_B/AGP bridge will be translated into Type 0 configuration cycles on the PCI_B/AGP
interface. The GMCH will decode the Device Number field [15:11] and assert the appropriate
GAD signal as an IDSEL in accordance with the PCI-to-PCI Bridge Type 0 configuration
mechanism.
If the Bus Number is non-zero, greater than the value programmed into the Secondary bus
number register, and less than or equal to the value programmed into the Subordinate bus number
register, the configuration cycle is targeting a PCI bus downstream of the targeted interface. The
GMCH will generate a Type 1 PCI configuration cycle on PCI_B/AGP.
To prepare for mapping of the configuration cycles on AGP/PCI_B, the initialization software
will go through the following sequence:
1. Scan all devices residing on the PCI Bus #0 using Type 0 configuration accesses.
2. For every device residing at bus #0 which implements PCI-to-PCI bridge functionality, it will
configure the secondary bus of the bridge with the appropriate number and scan further down
the hierarchy. This process will include the configuration of the “virtual” PCI-to-PCI bridges
within the GMCH used to map the AGP device’s address spaces in a software specific
manner.
Note: Although initial AGP platform implementations will not support hierarchical buses residing
below AGP, this specification still must define this capability in order to support PCI-66
compatibility. Note also that future implementations of the AGP devices may support hierarchical
PCI or AGP-like buses coming out of the root AGP device.
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