IA186EM_04 Datasheet, PDF (95/133 Pages) InnovASIC, Inc – 8/16-Bit Microcontrollers

IA186EM/IA188EM
8/16-BIT Microcontrollers
Data Sheet
As of Production Version -03
Numeric Key to Waveform Parameters
No. Name Description
No. Name Description
1 tDVCL Data in Setup
43 tCLCH clkoutA Low Time
2 tCLDX Data in Hold
44 tCHCL clkoutA High Time
3 tCHSV Status Active Delay
45 tCH1CH2 clkoutA Rise Time
4 tCLSH Status Inactive Delay
46 tCL2CL1 clkoutA Fall Time
5 tCLAV ad Address Valid Delay
47 tSRYCL srdy Transition Setup Time
6 tCLAX Address Hold
48 tCLSRY srdy Transistion Hold Time
7 tCLDV Data Valid Delay
49 tARYCH ardy Resolution Transition Setup Time
8 tCHDX Status Hold Time
50 tCLARX ardy Active Hold Time
9 tCHLH ale Active Delay
51 tARYCHL ardy Inactive Holding Time
10 tLHLL ale Width
52 tARYLCL ardy Setup Time
11 tCHLL ale Inactive Delay
53 tINVCH Peripheral Setup Time
12 tAVLL ad Address Valid to ALE Low
54 tINVCL drq Setup Time
13 tLLAX ad Address Hold from ALE Inactive
55 tCLTMV Timer Output Delay
14 tAVCH ad Address Valid to Clock High
57 tRESIN res_n Setup Time
15 tCLAZ ad Address Float Delay
58 tHVCL hld Setup Time
16 tCLCSV mcs_n/pcs_n Inactive Delay
59 tRHDX rd_n High to Data Hold on ad Bus
17 tCXCSX mcs_n/pcs_n Hold from Command Inactive 61 tLOCK Maximum PLL Lock Time
18 tCHCSX mcs_n/pcs_n Inactive Delay
62 tCLHAV hlda Valid Delay
19 tDXDL den_n Inactive to dt_r_n Low
63 tCHCZ Command Lines Float Delay
20 tCVCTV Control Active Delay 1
64 tCHCV Command Lines Valid Delay (after Float)
21 tCVDEX den_n Inactive Delay
65 tAVWL a Address Valid to wr_n Low
22 tCHCTV Control Active Delay 2
66 tAVRL a Address Valid to rd_n Low
23 tLHAV ale High to Address Valid
67 tCHCSV clkoutA High to lcs_n/usc_n Valid
24 tAZRL ad Address Float to rd_n Active
68 tCHAV clkoutA High to A Address Valid
25 tCLRL rd_n Active Delay
69 tCICOA X1 to clkoutA Skew
26 tRLRH rd_n Pulse Width
70 tCICOB X1 to clkoutB Skew
27 tCLRH rd_n Inactive Delay
71 tCLEV clkouta Low to sden Valid
28 tRHLH rd_n Inactive to ale High
72 tCLSL clkouta Low to sclk High
29 tRHAV rd_n Inactive to ad Address Active
75 tDVSH Data Valid to sclk High
30 tCLDOX Data Hold Time
77 tSHDX sclk High to SPI Data Hold
31 tCVCTX Control Inactive Delay
78 tSLDV sclk Low to Data Valid
32 tWLWH wr_n Pulse Width
79 tCHRFD clkoutA High to rfsh_n Valid
33 tWHLH wr_n Inactive to ale High
80 tCLCLX lcs_n Inactive Delay
34 tWHDX Data Hold after wr_n
81 tCLCSL lcs_n Active Delay
35 tWHDEX wr_n Inactive to den_n Inactive
82 tCLRF clkoutA High to rfsh_n Invalid
36 tCKIN X1 Period
83 tCOAOB clkoutA to clkoutB Skew
37 tCLCK X1 Low Time
84 tLRLL lcs_n Precharge Pulse Width
38 tCHCK X1 High Time
85 tRFCY rfsh_n Cycle Time
39 tCKHL X1 Fall Time
86 tLCRF lcs_n Inactive to rfsh_n Active Delay
40 tCKLH X1 Rise time
87 tAVBL a Address Valid to whb_n/wlb_n Low
42 tCLCL clkoutA Period
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