IA186EM_04 Datasheet, PDF (101/133 Pages) InnovASIC, Inc – 8/16-Bit Microcontrollers

IA186EM/IA188EM
8/16-BIT Microcontrollers
Data Sheet
As of Production Version -03
PSRAM Read Cycle Timing
No. Name
Comment
General Timing Requirements
1 tDVCL
Data in Setup
2 tCLDX
Data in Hold
General Timing Responses
5 tCLAV
ad Address Valid Delay
7 tCLDV
Data Valid Delay
8 tCHDX
Status Hold Time
9 tCHLH
ale Active Delay
10 tLHLL
11 tCHLL
23 tLHAV
80 tCLCLX
81 tCLCSL
ale Width
ale Inactive Delay
ale High to Address Valid
lcs_n Inactive Delay
lcs_n Active Delay
84 tLRLL
lcs_n Precharge Pulse Width
Read Cycle Timing Responses
24 tAZRL
ad Address Float to rd_n Active
25 tCLRL
rd_n Active Delay
26 tRLRH
rd_n Pulse Width
27 tCLRH
rd_n Inactive Delay
28 tRHLH
rd_n Inactive to ale High
59 tRHDX
rd_n High to Data Hold on ad Bus
66 tAVRL
68 tCHAV
a Address Valid to rd_n Low
clkoutA High to a Address Valid
MIN MAX Units
10 NLL ns
0
ns
0
12
ns
0
12
ns
0
ns
0
8
ns
tCHCL-
5
ns
0
8
ns
7.5
ns
0
9
ns
0
9
ns
tCLCL
+
tCLCH
ns
0
ns
0 10
ns
tCLCL
ns
0 10
ns
tCLCH
ns
0
ns
tCLCL
+
tCHCL
0
8
ns
3737 Princeton NE, Ste 130 • Albuquerque, NM 87107 • Tel [phone] • Fax [phone] • www.Innovasic.com