IA186EM_04 Datasheet, PDF (12/133 Pages) InnovASIC, Inc – 8/16-Bit Microcontrollers

IA186EM/IA188EM
8/16-BIT Microcontrollers
Data Sheet
As of Production Version -03
MDRAM (0e0h) - The Memory Partition Register holds the A19-A13 address bits of the 20-bit base
refresh address.
The MDRAM register contains 0000h at reset.
15 14
13
12
11
10
9 876543210
M [6:0]
000000000
M [6:0] (bits 15-9) – Upper bits corresponding to address bits a19-a13 of the 20-Bit memory refresh
address. These bits are not available on the a19-a0 bus. When using PSRAM mode, M6-M0 must be
programmed to 0000000b.
Reserved [8:0] (bits 8-0) – Reserved. These bits read back as 0.
D1CON (0dah) - DMA CONtrol Registers.
D0CON (0cah)
DMA Control Registers control operation of the two DMA channels. The D0CON and D1CON registers
are undefined at reset, except ST that is set to 0.
15
14
13
12
11 10 9 8 7 6 5 4
3 210
DM/IOn DDEC DINC SM/IOn SDEC SINC TC INT SYN1- P TDRQ Res CHG ST Bn/W
SYN0
DM/IOn (bit 15) – Destination Address Space Select selects memory or I/O space for the destination
address. When DM/IO is set to 1, the destination address is in memory space. When set to 0, the
destination address is in I/O space.
DDEC (bit 14) – Destination Decrement automatically decrements the destination address after each
transfer when set to 1. The address is decremented by 1 or 2, depending on the byte/word bit (Bn/W,
bit 0). The address does not change if the increment and decrement bits are set to the same value (00b
or 11b).
DINC (bit 13) – Destination Increment, when set to 1, automatically increments the destination
address after each transfer. The address is incremented by 1 or 2, depending on the byte/word bit
(Bn/W, bit 0). The address does not change if the increment and decrement bits are set to the same
value (00b or 11b).
SM/IOn (bit 12) – Source Address Space Select selects memory or I/O space for the source address.
When SM/IOn is set to 1, the source address is in memory space, while when 0, the source address is
in I/O space.
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