IA186EM_04 Datasheet, PDF (20/133 Pages) InnovASIC, Inc – 8/16-Bit Microcontrollers

IA186EM/IA188EM
8/16-BIT Microcontrollers
Data Sheet
As of Production Version -03
The value of the LMCS register is undefined at reset except DA, which is set to 0.
15 14
13 12 11 10 9 8 7 6 5 4 3 2 1 0
0
UB2 – UB0
1 1 1 1 DA PSE 1 1 1 R2 R1-R0
Reserved [15] (bit 15) – Set to 0
UB [2:0] (bits 14 – 12) - Upper Boundary. These bits define the upper boundary of memory accessed
by the lcs_n chip select. The following table gives the possible configurations of block size (max
512Kbytes).
LMCS Block Size Programming Values
Memory Block
Size
64K
128K
256K
512K
Ending
Address
0FFFFh
1FFFFh
3FFFFh
7FFFFh
UB2 – UB0
000b
001b
011b
111b
Reserved [11:8] (bits 11-8) - Set to 1.
DA (bit 7) Disable Address - When set to 0, the address is driven onto the address bus (ad15 – ad0)
during the address phase of a bus cycle. If DA is set to 1, the address bus is disabled, providing some
measure of power saving. This bit is set to 0 at reset.
If BHE_n/ADEN_n is held at 0 during the rising edge of res_n, then the address bus is always driven,
independent of the setting of DA.
PSE (bit 6) PSRAM Mode Enable – PSRAM support for the lcs_n chip select memory space is enabled
when the PSE is set to 1. The EDRAM, MDRAM, and CDRAM refresh control unit registers must be
configured for auto refresh before PSRAM support is enabled. Setting the enable bit (EN) in the
enable RCU register (EDRAM, offset e4h) configures the mcs3_n/rfsh_n as rfsh_n.
Reserved (bits 5-3) – Set to 1.
R2 (bit 2) - Ready Mode. When this bit is set to 0, an external ready is required. When set to 1, the
external ready is ignored. In either case, however, the value of the R1 - R0 bits determine the number
of wait states inserted.
R [1:0] (bits R1-R0) - Wait-State Value. The number of wait states inserted into an access to the
LCS_n memory area is determined by the value of these bits. This number ranges from 0 to 3 (R1 – R0
= 00b to 11b)
UMCS (0a0h) - Upper Memory Chip Select Register configures the Upper Memory Chip Select pin,
which is used for the top of memory. On reset, the first fetch takes place at memory location FFFF0h and
thus this area of memory is usually used for instruction memory. With this in mind, UCS_n defaults to an
3737 Princeton NE, Ste 130 • Albuquerque, NM 87107 • Tel [phone] • Fax [phone] • www.Innovasic.com