IA186EM_04 Datasheet, PDF (92/133 Pages) InnovASIC, Inc – 8/16-Bit Microcontrollers

IA186EM/IA188EM
8/16-BIT Microcontrollers
Data Sheet
As of Production Version -03
No. Name
34 tWHDX
35 tWHDEX
41 tDSHLH
59 tRHDX
65 tAVWL
Description
Data Hold after wr_n
wr_n Inactive to den_n Inactive
ds_n Inactive to ale Inactive
rd_n High to Data Hold on ad Bus
a Address Valid to wr_n Low
66 tAVRL
67 tCHCSV
68 tCHAV
87 tAVBL
a Address Valid to rd_n Low
clkoutA High to lcs_n/usc_n Valid
clkoutA High to a Address Valid
a Address Valid to whb_n/wlb_n Low
Refresh Timing Cycle Parameters
79 tCHRFD
clkoutA High to rfsh_n Valid
82 tCLRF
85 tRFCY
clkoutA High to rfsh_n Invalid
rfsh_n Cycle Time
86 tLCRF
lcs_n Inactive to rfsh_n Active Delay
clkin Timing
36 tCKIN
X1 Period
37 tCLCK
X1 Low Time
38 tCHCK
X1 High Time
39 tCKHL
X1 Fall Time
40 tCKLH
clkout Timing
X1 Rise time
42 tCLCL
clkoutA Period
43 tCLCH
clkoutA Low Time
44 tCHCL
clkoutA High Time
45 tCH1CH2
clkoutA Rise Time
46 tCL2CL1
clkoutA Fall Time
61 tLOCK
Maximum PLL Lock Time
69 tCICOA
X1 to clkoutA Skew
70 tCICOB
X1 to clkoutB Skew
Ready & Peripheral Timing Requirements
47 tSRYCL
srdy Transition Setup Time
48 tCLSRY
srdy Transistion Hold Time
49 tARYCH
ardy Resolution Transition Setup Time
50 tCLARX
ardy Active Hold Time
51 tARYCHL
ardy Inactive Holding Time
52 tARYLCL
ardy Setup Time
53 tINVCH
Peripheral Setup Time
54 tINVCL
drq Setup Time
MIN MAX
tCLCL
tCLCH
tCLCH
0
tCLCL +
tCHCL
tCLCL +
tCHCL
0
9
0
8
tCHCL -
1.5 tCHCL
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
0
12
ns
0
12
ns
6tCLCL
ns
2tCLCL
ns
25
66
ns
7.5
ns
7.5
ns
5
ns
5
ns
25
ns
TCLCL/2
ns
TCLCL/2
ns
3
ns
3
ns
0.5
ms
25
ns
35
ns
10
ns
3
ns
9
ns
4
ns
6
ns
9
ns
10
ns
10
ns
3737 Princeton NE, Ste 130 • Albuquerque, NM 87107 • Tel [phone] • Fax [phone] • www.Innovasic.com