IA186EM_04 Datasheet, PDF (30/133 Pages) InnovASIC, Inc – 8/16-Bit Microcontrollers

IA186EM/IA188EM
8/16-BIT Microcontrollers
Data Sheet
As of Production Version -03
PMODE [15:0] (bits 15-0) – PIO Mode 0 Bits. For each bit, if the value is 1 then the pin is
configured as an input and as an output if the value is 0. The values of these bits correspond to those
in the PIO data registers and PIO Mode registers.
PMODE [31:16] (bits 15-0) – PIO Mode 1 Bits. For each bit, if the value is 1 then the pin is
configured as an input and as an output if the value is 0. The values of these bits correspond to those
in the PIO data registers and PIO Mode registers.
T1CON (05eh) - Timer 0 and Timer 1 Mode and CONtrol Registers.
T0CON (056h)
This registers controls the operation of the Timer 1 and Timer 0 respectively.
The value of both the T0CON and T1CON registers is 0000h at reset.
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EN INHn INT RIU 0 0 0 0 0 0 MC RTG P EXT ALT CONT
EN (bit 15) – Enable Bit. The timer is enabled when the EN bit is 1. The timer count is inhibited
when the EN bit is 0. This bit is write-only, but with the INHn bit set to 1 in the same write operation.
INHn (bit 14) – Inhibit Bit. Gates the setting of the enable (EN) bit. This bit must be set to 1 in the
same write operation that sets the enable (EN) bit. Otherwise, the EN bit will not be changed. This bit
always reads as 0.
INT (bit 13) – Interrupt Bit. An interrupt request is generated when the Count register reaches its
maximum, MC = 1, by setting the INT bit to 1. In dual maxcount mode, an interrupt request is
generated when the count register reaches the value in maxcount A or maxcount B. No interrupt
requests are generated if this bit is set to 0. If an interrupt request is generated and then the enable bit
is cleared before said interrupt is serviced, the interrupt request will remain.
RIU (bit 12) – Register in Use Bit. This bit is set to 1 when the maxcount register B is used to
compare to the timer count value. It is set to 0 when the maxcount compare A register is used.
Reserved (bits 11-6) – Set to 0.
MC (bit 5) – Maximum Count. When the timer reaches its maximum count this bit is set to 1
regardless of the interrupt enable bit. This bit is also set every time Maxcount Compare register A or
B is reached, when in dual maxcount mode. This bit may be used by software polling to monitor
timer status rather than through interrupts if desired.
RTG (bit 4) – Retrigger Bit. This pin controls the timer function of the timer input pin. When set to 1,
the count is reset by a 0 to 1 transition on timrin0 or tmrin1. When set to 0, a high input on tmrin0
or tmrin1 enables the count and a 1 holds the timer value. This bit is ignored if the external clocking
(EXT=1) bit is set.
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