IA186EM_04 Datasheet, PDF (17/133 Pages) InnovASIC, Inc – 8/16-Bit Microcontrollers

IA186EM/IA188EM
8/16-BIT Microcontrollers
Data Sheet
As of Production Version -03
MS (bit 6) Memory/ I/O Space Selector determines whether the pcs_n pins are active either during
memory or I/O bus cycles. When MS is set to 1, the pcs_n outputs are active for memory bus cycles,
and active for I/O bus cycles when set to 0.
Reserved (bits 5:3) – Set to 1.
R2 (bit 2) Ready Mode – This bit influences only the pcs6_n - pcs5_n chip selects. If R2 is set to 0,
external ready is required. If R2 is set to 1, external ready is ignored. In each case, the values of the
R1-R0 bits determine the number of wait states to be inserted.
R [1:0] (bits 1-0) Wait-State Value – These bits influence only the pcs6_n - pcs5_n chip selects. The
value of R1-R0 determines the number of wait states inserted into an access depending on whether its
to the PCS_n memory or I/O area. Up to three wait states can be inserted (R1 - R0 = 00b to 11b).
MMCS (0a6h) - Midrange Memory Chip Select Register.
Four chip-select pins, mcs3_n - mcs0_n, are provided for use within a user-locatable memory block. The
memory block base address can be located anywhere within the 1-Mbyte memory address space,
excluding the areas associated with the ucs_n and lcs_n chip selects (and, if mapped to memory, the
address range of the Peripheral Chip Selects, pcs6_n - pcs5_n and pcs3_n to pcs0_n). If the pcs_n chip
selects are mapped to I/O space, the mcs_n address range can overlap the pcs_n address range
Two registers program the Midrange Chip Selects. The Midrange Memory Chip Select (MMCS) register
determines the base address, the ready condition and wait states of the memory block that are accessed
through the mcs_n pins. The pcs_n and mcs_n Auxiliary (MPCS) register configures the block size. On
reset the mcs3_n - mcs0_n pins are not active. Accessing with a write both the MMCS and MPCS
registers activates these chip selects.
The mcs3_n - mcs0_n outputs assert with the multiplexed AD address bus (ad15 – ad0 or ao15 – ao8
and ad7 – ad0) rather than the earlier timing of the a19 – a0 bus unlike the ucs_n and lcs_n chip selects.
The timing is delayed for a half cycle later than that for ucs_n and lcs_n if the a19 – a0 bus is used for
address selection.
The value of the MMCS register is undefined at reset.
15
14
13 12 11 10 9 8 7 6 5 4 3 2 1 0
BA19 – BA13
1 1 1 1 1 1 R2 R1 - R0
BA [15:9] (bits 15-9) – Base Address. The value of the BA19 – BA13 determines the Base Address of
the memory block that is addressed by the mcs_n chip select pins. These bits correspond to bits a19 –
a13 of the 20-bit memory address. The remaining bits a12 – a0 of the base address are always 0.
The base address may be any integer multiple of the size of the memory clock selected in the MPCS
register. For example, if the midrange block is 32 Kbytes, the block could be located at 20000h or
28000h but not at 24000h.
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