IA186EM_04 Datasheet, PDF (18/133 Pages) InnovASIC, Inc – 8/16-Bit Microcontrollers

IA186EM/IA188EM
8/16-BIT Microcontrollers
Data Sheet
As of Production Version -03
If the lcs_n chip select is inactive, the base address of the midrange chip selects can be set to 00000h,
because the lcs_n chip select is defined to be 00000h but is unused. The further limitation that the
base address must be an integer multiple of the block size means that a 512K MMCS block size can
only be used with the lcs_n chip select inactive and the base address of the midrange chip selects set
to 00000h.
Reserved [8:3] (bits 8-3) - Set to 1.
R2 (bit 2) – Ready mode. This bit determines the mcs_n chip selects ready mode. When R2 is 0, an
external ready is necessary. If R2 is 1, an external ready is ignored. In each case, the number of wait
states inserted in an access is determined by the value of the R1 & R0 bits.
R [1:0] (bits 1-0) – Wait-State Value. The number of wait states inserted in an access is determined
by the value of the R1 & R0 bits. Up to three wait states can be inserted (R1 - R0 = 00b to 11b).
PACS (0a4h) - PeripherAl Chip Select Register.
The Peripheral Chip Selects are asserted over 256-byte range with the same timing as the AD address bus.
There are six chip selects, pcs6_n - pcs5_n and pcs3_n - pcs0_n, that are utilized in either the user-
locatable memory or I/O blocks. The pcs4_n chip select is not implemented in the ia18xEM family of
Micro controllers. Excluding the areas utilized by the ucs_n, lcs_n, and mcs_n chip selects, the memory
block can be located anywhere within the 1-Mbyte address space. These chip selects may also be
configured to access the 64-Kbyte I/O space.
Programming the Peripheral Chip Selects uses two registers, The Peripheral Chip Select (PACS) register
and the pcs_n and mcs_n Auxiliary (MPCS) register. The PACS register establishes the base address,
configures the ready mode, and determines the number of wait states for the pcs3_n - pcs0_n outputs.
The MPCS register configures the pcs6_n – pcs5_n pins to be either chip selects or address pins a1 and
a2. When these pins are configured as chip selects, the MPCS register determines whether they are active
during memory or I/O bus cycles and determines the ready state and wait states for these output pins.
These pins are not active on reset but are activated as chip selects by writing to the two registers (PACS
and MPCS). To configure and activate them as address pins it is necessary to write to both the PACS and
MPCS registers. pcs6_n – pcs5_n can be configured for 0 to 3 wait states while pcs3_n - pcs0_n can be
programmed for 0 to 15 wait states.
The value of the PACS register is undefined at reset.
15
14
13 12 11 10 9 8 7 6 5 4 3 2 1 0
BA19 – BA11
1 1 1 R3 R2 R1 –R0
BA [19:11] (bits 15-7) - Base Address bits determine the base address and correspond to bits 19 - 11
of the 20-bit programmable base address of the peripheral chip select block. However, if the PCS_n
chip selects are mapped to I/O space, these bits must be set to 0000b, as I/O addresses are only 16 bits
wide.
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